From e32fa4e152b212bf1d886b2007b01521a7161cbc Mon Sep 17 00:00:00 2001 From: Felix Singer Date: Tue, 11 Aug 2020 06:57:44 +0200 Subject: soc/intel/skylake: Refactor PEG configuration MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit Simplify some if-blocks which are used for the configuration, enablement and disablement of the PEG devices. This changes the logic of the code, since it configures PegxEnable before the if-blocks, where x is the number of the PEG device, and the further configuration of the PEG devices depends on the enablement of PegxEnable. Change-Id: I6dd88ce752ce8f0255c424d0e5b2d8ef918885a1 Signed-off-by: Felix Singer Reviewed-on: https://review.coreboot.org/c/coreboot/+/44368 Tested-by: build bot (Jenkins) Reviewed-by: Angel Pons Reviewed-by: Michael Niewöhner --- src/soc/intel/skylake/romstage/romstage.c | 18 ++++++------------ 1 file changed, 6 insertions(+), 12 deletions(-) (limited to 'src/soc/intel/skylake/romstage') diff --git a/src/soc/intel/skylake/romstage/romstage.c b/src/soc/intel/skylake/romstage/romstage.c index 9add1e688f..cefe7426e4 100644 --- a/src/soc/intel/skylake/romstage/romstage.c +++ b/src/soc/intel/skylake/romstage/romstage.c @@ -171,10 +171,8 @@ static void soc_peg_init_params(FSP_M_CONFIG *m_cfg, * in FSP */ dev = pcidev_path_on_root(SA_DEVFN_PEG0); /* PEG 0:1:0 */ - if (!dev || !dev->enabled) - m_cfg->Peg0Enable = 0; - else if (dev->enabled) { - m_cfg->Peg0Enable = dev->enabled; + m_cfg->Peg0Enable = dev && dev->enabled; + if (m_cfg->Peg0Enable) { m_cfg->Peg0MaxLinkWidth = config->Peg0MaxLinkWidth; /* Use maximum possible link speed */ m_cfg->Peg0MaxLinkSpeed = 0; @@ -186,10 +184,8 @@ static void soc_peg_init_params(FSP_M_CONFIG *m_cfg, } dev = pcidev_path_on_root(SA_DEVFN_PEG1); /* PEG 0:1:1 */ - if (!dev || !dev->enabled) - m_cfg->Peg1Enable = 0; - else if (dev->enabled) { - m_cfg->Peg1Enable = dev->enabled; + m_cfg->Peg1Enable = dev && dev->enabled; + if (m_cfg->Peg1Enable) { m_cfg->Peg1MaxLinkWidth = config->Peg1MaxLinkWidth; m_cfg->Peg1MaxLinkSpeed = 0; m_cfg->Peg1PowerDownUnusedLanes = 1; @@ -198,10 +194,8 @@ static void soc_peg_init_params(FSP_M_CONFIG *m_cfg, } dev = pcidev_path_on_root(SA_DEVFN_PEG2); /* PEG 0:1:2 */ - if (!dev || !dev->enabled) - m_cfg->Peg2Enable = 0; - else if (dev->enabled) { - m_cfg->Peg2Enable = dev->enabled; + m_cfg->Peg2Enable = dev && dev->enabled; + if (m_cfg->Peg2Enable) { m_cfg->Peg2MaxLinkWidth = config->Peg2MaxLinkWidth; m_cfg->Peg2MaxLinkSpeed = 0; m_cfg->Peg2PowerDownUnusedLanes = 1; -- cgit v1.2.3