From c3385070d6e86dbde71dddbdef94ffa5579f9d11 Mon Sep 17 00:00:00 2001
From: Elyes HAOUAS <ehaouas@noos.fr>
Date: Thu, 21 Mar 2019 15:38:06 +0100
Subject: soc/{amd,intel}/chip: Use local include for chip.h

Change-Id: Ic1fcbf4b54b7d0b5cda04ca9f7fc145050c867b8
Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/32014
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Nico Huber <nico.h@gmx.de>
---
 src/soc/intel/skylake/romstage/romstage.c       | 3 ++-
 src/soc/intel/skylake/romstage/romstage_fsp20.c | 3 ++-
 2 files changed, 4 insertions(+), 2 deletions(-)

(limited to 'src/soc/intel/skylake/romstage')

diff --git a/src/soc/intel/skylake/romstage/romstage.c b/src/soc/intel/skylake/romstage/romstage.c
index d8188f6924..0501b04493 100644
--- a/src/soc/intel/skylake/romstage/romstage.c
+++ b/src/soc/intel/skylake/romstage/romstage.c
@@ -17,7 +17,6 @@
 #include <arch/cbfs.h>
 #include <arch/early_variables.h>
 #include <assert.h>
-#include <chip.h>
 #include <console/console.h>
 #include <cpu/x86/mtrr.h>
 #include <device/device.h>
@@ -37,6 +36,8 @@
 #include <stdint.h>
 #include <vendorcode/google/chromeos/chromeos.h>
 
+#include "../chip.h"
+
 /* SOC initialization before RAM is enabled */
 void soc_pre_ram_init(struct romstage_params *params)
 {
diff --git a/src/soc/intel/skylake/romstage/romstage_fsp20.c b/src/soc/intel/skylake/romstage/romstage_fsp20.c
index dcfc3632ca..1e81d7aa05 100644
--- a/src/soc/intel/skylake/romstage/romstage_fsp20.c
+++ b/src/soc/intel/skylake/romstage/romstage_fsp20.c
@@ -20,7 +20,6 @@
 #include <cpu/x86/mtrr.h>
 #include <cpu/x86/msr.h>
 #include <cbmem.h>
-#include <chip.h>
 #include <console/console.h>
 #include <device/pci_def.h>
 #include <fsp/util.h>
@@ -37,6 +36,8 @@
 #include <timestamp.h>
 #include <security/vboot/vboot_common.h>
 
+#include "../chip.h"
+
 #define FSP_SMBIOS_MEMORY_INFO_GUID	\
 {	\
 	0xd4, 0x71, 0x20, 0x9b, 0x54, 0xb0, 0x0c, 0x4e,	\
-- 
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