From 9593e973fa0e3a104837d1df9659b3992d915b34 Mon Sep 17 00:00:00 2001 From: Nico Huber Date: Sun, 27 May 2018 14:01:11 +0200 Subject: soc/{amd,intel}: Use CACHE_ROM_(BASE|SIZE) Boards could choose a high ROM_SIZE that would result in an MTRR config that conflicts with other resources. Thus, always use the filtered CACHE_ROM_SIZE. Change-Id: I66d36b84ce49c1cb98cb36a4731977baaedf3225 Signed-off-by: Nico Huber Reviewed-on: https://review.coreboot.org/26575 Reviewed-by: Aaron Durbin Tested-by: build bot (Jenkins) --- src/soc/intel/skylake/romstage/romstage_fsp20.c | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) (limited to 'src/soc/intel/skylake/romstage') diff --git a/src/soc/intel/skylake/romstage/romstage_fsp20.c b/src/soc/intel/skylake/romstage/romstage_fsp20.c index 760dcc1e8c..a93407620b 100644 --- a/src/soc/intel/skylake/romstage/romstage_fsp20.c +++ b/src/soc/intel/skylake/romstage/romstage_fsp20.c @@ -186,8 +186,8 @@ asmlinkage void car_stage_entry(void) } /* Cache the ROM as WP just below 4GiB. */ - postcar_frame_add_mtrr(&pcf, 0xFFFFFFFF - CONFIG_ROM_SIZE + 1, - CONFIG_ROM_SIZE, MTRR_TYPE_WRPROT); + postcar_frame_add_mtrr(&pcf, CACHE_ROM_BASE, CACHE_ROM_SIZE, + MTRR_TYPE_WRPROT); run_postcar_phase(&pcf); } -- cgit v1.2.3