From 46a71782678b17aec49e938ab941a2604a5b9afe Mon Sep 17 00:00:00 2001
From: Subrata Banik <subrata.banik@intel.com>
Date: Fri, 2 Jun 2017 18:52:24 +0530
Subject: soc/intel/skylake: Use common systemagent code

This patch perform resource mapping for PCI,
fixed MMIO, DRAM and IMR's based on inputs given by SoC.

TEST=Ensure PCI root bridge 0:0:0 memory resource allocation
remains same between previous implementation and current
implementation.

Change-Id: I93567a79b2d12dd5d6363957e55ce2cb86ff83a7
Signed-off-by: Subrata Banik <subrata.banik@intel.com>
Reviewed-on: https://review.coreboot.org/19796
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
---
 src/soc/intel/skylake/romstage/systemagent.c | 49 ++++++++++++----------------
 1 file changed, 21 insertions(+), 28 deletions(-)

(limited to 'src/soc/intel/skylake/romstage')

diff --git a/src/soc/intel/skylake/romstage/systemagent.c b/src/soc/intel/skylake/romstage/systemagent.c
index 2f58db6961..8f2fb337ed 100644
--- a/src/soc/intel/skylake/romstage/systemagent.c
+++ b/src/soc/intel/skylake/romstage/systemagent.c
@@ -15,38 +15,31 @@
  * GNU General Public License for more details.
  */
 
-#include <stdlib.h>
-#include <arch/io.h>
-#include <device/pci_def.h>
-#include <reg_script.h>
+#include <device/device.h>
+#include <intelblocks/systemagent.h>
 #include <soc/iomap.h>
-#include <soc/pci_devs.h>
 #include <soc/romstage.h>
 #include <soc/systemagent.h>
 
-static const struct reg_script systemagent_early_init_script[] = {
-	REG_PCI_WRITE32(MCHBAR, MCH_BASE_ADDRESS | 1),
-	REG_PCI_WRITE32(DMIBAR, DMI_BASE_ADDRESS | 1),
-	REG_PCI_WRITE32(EPBAR, EP_BASE_ADDRESS | 1),
-	REG_MMIO_WRITE32(MCH_BASE_ADDRESS + EDRAMBAR, EDRAM_BASE_ADDRESS | 1),
-	REG_MMIO_WRITE32(MCH_BASE_ADDRESS + GDXCBAR, GDXC_BASE_ADDRESS | 1),
-
-	/* Set C0000-FFFFF to access RAM on both reads and writes */
-	REG_PCI_WRITE8(PAM0, 0x30),
-	REG_PCI_WRITE8(PAM1, 0x33),
-	REG_PCI_WRITE8(PAM2, 0x33),
-	REG_PCI_WRITE8(PAM3, 0x33),
-	REG_PCI_WRITE8(PAM4, 0x33),
-	REG_PCI_WRITE8(PAM5, 0x33),
-	REG_PCI_WRITE8(PAM6, 0x33),
-
-	/* Device enable: IGD and Mini-HD */
-	REG_PCI_WRITE32(DEVEN, DEVEN_D0EN | DEVEN_D2EN | DEVEN_D3EN),
-
-	REG_SCRIPT_END
-};
-
 void systemagent_early_init(void)
 {
-	reg_script_run_on_dev(SA_DEV_ROOT, systemagent_early_init_script);
+	static const struct sa_mmio_descriptor soc_fixed_pci_resources[] = {
+		{ MCHBAR, MCH_BASE_ADDRESS, MCH_BASE_SIZE, "MCHBAR" },
+		{ DMIBAR, DMI_BASE_ADDRESS, DMI_BASE_SIZE, "DMIBAR" },
+		{ EPBAR, EP_BASE_ADDRESS, EP_BASE_SIZE, "EPBAR" },
+	};
+
+	static const struct sa_mmio_descriptor soc_fixed_mch_resources[] = {
+		{ GDXCBAR, GDXC_BASE_ADDRESS, GDXC_BASE_SIZE, "GDXCBAR" },
+		{ EDRAMBAR, EDRAM_BASE_ADDRESS, EDRAM_BASE_SIZE, "EDRAMBAR" },
+	};
+
+	/* Set Fixed MMIO addresss into PCI configuration space */
+	sa_set_pci_bar(soc_fixed_pci_resources,
+			ARRAY_SIZE(soc_fixed_pci_resources));
+	/* Set Fixed MMIO addresss into MCH base address */
+	sa_set_mch_bar(soc_fixed_mch_resources,
+			ARRAY_SIZE(soc_fixed_mch_resources));
+	/* Enable PAM regisers */
+	enable_pam_region();
 }
-- 
cgit v1.2.3