From e6af4be1587f34f2f79d6e8b9ece94cfa7cd4c8e Mon Sep 17 00:00:00 2001 From: Aaron Durbin Date: Thu, 24 Sep 2015 12:26:31 -0500 Subject: intel fsp1_1: prepare for romstage vboot verification split In order to introduce a verstage which performs vboot verification the cache-as-ram environment needs to be generalized and split into pieces that can be utilized in romstage and/or verstage. Therefore, the romstage pieces were removed from the cache-as-ram specific pieces that are generic: - Add fsp/car.h to house the declarations for functions in the cache-as-ram environment - Only have cache_as_ram_params which are isolated form the cache-as-ram environment aside from FSP_INFO_HEADER. - Hardware requirements for console initialization is done in the cache-as-ram specific files. - Provide after_raminit.S which can be included from a romstage separated from cache-as-ram as well as one that is tightly coupled to the cache-as-ram environment. - Update the fallout from the API changes in soc/intel/{braswell,common,skylake}. BUG=chrome-os-partner:44827 BRANCH=None TEST=Built and booted glados. Original-Change-Id: I2fb93dfebd7d9213365a8b0e811854fde80c973a Original-Signed-off-by: Aaron Durbin Original-Reviewed-on: https://chromium-review.googlesource.com/302481 Original-Reviewed-by: Duncan Laurie Change-Id: Id93089b7c699dd6d83fed8831a7e275410f05afe Signed-off-by: Aaron Durbin Reviewed-on: http://review.coreboot.org/11816 Tested-by: build bot (Jenkins) Reviewed-by: Patrick Georgi --- src/soc/intel/skylake/romstage/romstage.c | 20 ++++++++++---------- 1 file changed, 10 insertions(+), 10 deletions(-) (limited to 'src/soc/intel/skylake/romstage/romstage.c') diff --git a/src/soc/intel/skylake/romstage/romstage.c b/src/soc/intel/skylake/romstage/romstage.c index 922062610a..b21eb8a304 100644 --- a/src/soc/intel/skylake/romstage/romstage.c +++ b/src/soc/intel/skylake/romstage/romstage.c @@ -46,8 +46,15 @@ #include #include -/* SOC initialization before the console is enabled */ -void soc_pre_console_init(void) +/* SOC initialization before RAM is enabled */ +void soc_pre_ram_init(struct romstage_params *params) +{ + /* Prepare to initialize memory */ + soc_fill_pei_data(params->pei_data); +} + +/* SOC initialization before the console is enabled. */ +void car_soc_pre_console_init(void) { /* System Agent Early Initialization */ systemagent_early_init(); @@ -56,14 +63,7 @@ void soc_pre_console_init(void) pch_uart_init(); } -/* SOC initialization before RAM is enabled */ -void soc_pre_ram_init(struct romstage_params *params) -{ - /* Prepare to initialize memory */ - soc_fill_pei_data(params->pei_data); -} - -void soc_romstage_init(struct romstage_params *params) +void car_soc_post_console_init(void) { report_platform_info(); set_max_freq(); -- cgit v1.2.3