From 9dcd4f059b5ba5229c90385e3d384ec04cc734f5 Mon Sep 17 00:00:00 2001 From: Duncan Laurie Date: Mon, 17 Aug 2015 18:09:14 -0700 Subject: fsp raminit: Add romstage_params to soc_memory_init_params The SOC handler for memory init params is only taking UPD as an input which does not allow it to use romstage_params. In addition the UPD input is called params which is confusing so rename it to upd so romstage_params can be passed properly. BUG=chrome-os-partner:40635 BRANCH=none TEST=build and boot on glados p2 Change-Id: I414610fee2b5d03a8e2cebfa548ea8bf49932a48 Signed-off-by: Patrick Georgi Original-Commit-Id: db94d6f3e6cad721de2188a136df10ccf66aff6a Original-Change-Id: I7ec15edd4a16df121c5967aadd8b2651267ec773 Original-Signed-off-by: Duncan Laurie Original-Reviewed-on: https://chromium-review.googlesource.com/294066 Original-Reviewed-by: Aaron Durbin Reviewed-on: http://review.coreboot.org/11413 Tested-by: build bot (Jenkins) Reviewed-by: Aaron Durbin --- src/soc/intel/skylake/romstage/romstage.c | 36 +++++++++++++++---------------- 1 file changed, 18 insertions(+), 18 deletions(-) (limited to 'src/soc/intel/skylake/romstage/romstage.c') diff --git a/src/soc/intel/skylake/romstage/romstage.c b/src/soc/intel/skylake/romstage/romstage.c index 2ce5ce35f1..91a496eb52 100644 --- a/src/soc/intel/skylake/romstage/romstage.c +++ b/src/soc/intel/skylake/romstage/romstage.c @@ -77,33 +77,33 @@ int vboot_get_sw_write_protect(void) #endif /* UPD parameters to be initialized before MemoryInit */ -void soc_memory_init_params(MEMORY_INIT_UPD *params) +void soc_memory_init_params(struct romstage_params *params, + MEMORY_INIT_UPD *upd) { const struct device *dev; const struct soc_intel_skylake_config *config; - /* Set the parameters for MemoryInit */ dev = dev_find_slot(0, PCI_DEVFN(PCH_DEV_SLOT_LPC, 0)); config = dev->chip_info; - memcpy(params->PcieRpEnable, config->PcieRpEnable, - sizeof(params->PcieRpEnable)); - memcpy(params->PcieRpClkReqSupport, config->PcieRpClkReqSupport, - sizeof(params->PcieRpClkReqSupport)); - memcpy(params->PcieRpClkReqNumber, config->PcieRpClkReqNumber, - sizeof(params->PcieRpClkReqNumber)); + memcpy(upd->PcieRpEnable, config->PcieRpEnable, + sizeof(upd->PcieRpEnable)); + memcpy(upd->PcieRpClkReqSupport, config->PcieRpClkReqSupport, + sizeof(upd->PcieRpClkReqSupport)); + memcpy(upd->PcieRpClkReqNumber, config->PcieRpClkReqNumber, + sizeof(upd->PcieRpClkReqNumber)); - params->MmioSize = 0x800; /* 2GB in MB */ - params->TsegSize = CONFIG_SMM_TSEG_SIZE; - params->IedSize = CONFIG_IED_REGION_SIZE; - params->ProbelessTrace = config->ProbelessTrace; - params->EnableLan = config->EnableLan; - params->EnableSata = config->EnableSata; - params->SataMode = config->SataMode; - params->EnableTraceHub = config->EnableTraceHub; - params->SaGv = config->SaGv; - params->RMT = config->Rmt; + upd->MmioSize = 0x800; /* 2GB in MB */ + upd->TsegSize = CONFIG_SMM_TSEG_SIZE; + upd->IedSize = CONFIG_IED_REGION_SIZE; + upd->ProbelessTrace = config->ProbelessTrace; + upd->EnableLan = config->EnableLan; + upd->EnableSata = config->EnableSata; + upd->SataMode = config->SataMode; + upd->EnableTraceHub = config->EnableTraceHub; + upd->SaGv = config->SaGv; + upd->RMT = config->Rmt; } void soc_display_memory_init_params(const MEMORY_INIT_UPD *old, -- cgit v1.2.3