From 5c56ce13f4a81970ed8c9a2987c2ea55376da52d Mon Sep 17 00:00:00 2001 From: Naveen Krishna Chatradhi Date: Wed, 15 Jul 2015 16:02:25 +0530 Subject: Skylake: Only support UART2 as debug port, clean up the rest On Skylake, only UART2 is supported as debug port and the macros INTEL_PCH_UART_CONSOLE_NUMBER, INTEL_PCH_UART_CONSOLE and the partial code for UART0, 1 are cleaned up for Skylake and Sklrvp, Kunimitsu and Glados boards. BRANCH=none BUG=chrome-os-partner:40857 TEST=Built for kunimitsu, checked the coreboot logs on LPSS UART2 Change-Id: I2fbcfb1d1ca6f59309a77c67d022cf4f5da7f7c0 Signed-off-by: Patrick Georgi Original-Commit-Id: e714c18d462bc7bdd7068309fb6be77da6973642 Original-Change-Id: I9343abd90ce685ea2d676047dccbefad7457b69f Original-Signed-off-by: Naveen Krishna Chatradhi Original-Reviewed-on: https://chromium-review.googlesource.com/285793 Original-Reviewed-by: Aaron Durbin Original-Commit-Queue: Wenkai Du Original-Tested-by: Wenkai Du Reviewed-on: http://review.coreboot.org/10994 Tested-by: build bot (Jenkins) Reviewed-by: Stefan Reinauer --- src/soc/intel/skylake/romstage/romstage.c | 3 +-- 1 file changed, 1 insertion(+), 2 deletions(-) (limited to 'src/soc/intel/skylake/romstage/romstage.c') diff --git a/src/soc/intel/skylake/romstage/romstage.c b/src/soc/intel/skylake/romstage/romstage.c index 4230664911..919b747211 100644 --- a/src/soc/intel/skylake/romstage/romstage.c +++ b/src/soc/intel/skylake/romstage/romstage.c @@ -50,8 +50,7 @@ void soc_pre_console_init(struct romstage_params *params) /* System Agent Early Initialization */ systemagent_early_init(); - if (IS_ENABLED(CONFIG_INTEL_PCH_UART_CONSOLE)) - pch_uart_init(); + pch_uart_init(); } /* SOC initialization before RAM is enabled */ -- cgit v1.2.3