From 5bf42c6c23b462d9292e6854d3f334cf17e42825 Mon Sep 17 00:00:00 2001 From: Barnali Sarkar Date: Wed, 24 Aug 2016 20:48:46 +0530 Subject: soc/intel/skylake: Add FSP 2.0 support in romstage Populate SoC related Memory initialization params. Post memory init, set DISB, setup stack and MTRRs using the postcar funtions provided in postcar_loader.c. TEST=Build and boot kunimitsu, dram initialization done. ramstage is loaded. Change-Id: I8d943e29b6e118986189166d92c7891ab6642193 Signed-off-by: Rizwan Qureshi Signed-off-by: Naresh G Solanki Reviewed-on: https://review.coreboot.org/16315 Tested-by: build bot (Jenkins) Reviewed-by: Aaron Durbin --- src/soc/intel/skylake/romstage/romstage.c | 8 +------- 1 file changed, 1 insertion(+), 7 deletions(-) (limited to 'src/soc/intel/skylake/romstage/romstage.c') diff --git a/src/soc/intel/skylake/romstage/romstage.c b/src/soc/intel/skylake/romstage/romstage.c index 0ec2f99e63..97c6a4526e 100644 --- a/src/soc/intel/skylake/romstage/romstage.c +++ b/src/soc/intel/skylake/romstage/romstage.c @@ -243,11 +243,5 @@ void soc_after_ram_init(struct romstage_params *params) /* Set the DISB as soon as possible after DRAM * init and MRC cache is saved. */ - u32 disb_val = 0; - device_t dev = PCH_DEV_PMC; - disb_val = pci_read_config32(dev, GEN_PMCON_A); - disb_val |= DISB; - /* Preserve bits which get cleared up if written 1 */ - disb_val &= ~(GBL_RST_STS | MS4V); - pci_write_config32(dev, GEN_PMCON_A, disb_val); + pmc_set_disb(); } -- cgit v1.2.3