From 3ad63565a54f5ea3cdd866cbc6c70c67ad2757fe Mon Sep 17 00:00:00 2001 From: Rizwan Qureshi Date: Sun, 14 Aug 2016 15:48:33 +0530 Subject: soc/intel/skylake: Correct Cache as ram size DCACHE_RAM_SIZE_TOTAL is set to 0x40000 and is being used to set up CAR. Whereas DCACHE_RAM_SIZE which is set to 0x10000 is used to calculate the _car_region_end in car.ld. If the FSP CAR requirement is greater than or even close to DCACHE_RAM_SIZE then, the CAR region for FSP will be determined to be below the overall CAR region boundary i.e, out of CAR memory range. This is working with FSP 1.1 because we provide the FspCarSize and FspCarBase explicitly in a UPD. Hence, FSP is still able to use the upper region of CAR memory for its purpose. However, it will be a problem in case of FSP2.0 where FSP usable CAR is calculated using _car_region_end. So, Remove the the use of DCACHE_RAM_SIZE_TOTAL and set DCACHE_RAM_SIZE to correct value i.e, 0x40000(256KB) Change-Id: Ie2cb8bb0705a37edb3414850d7659f8a3dd6958b Signed-off-by: Rizwan Qureshi Reviewed-on: https://review.coreboot.org/16236 Reviewed-by: Martin Roth Tested-by: build bot (Jenkins) --- src/soc/intel/skylake/romstage/romstage.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) (limited to 'src/soc/intel/skylake/romstage/romstage.c') diff --git a/src/soc/intel/skylake/romstage/romstage.c b/src/soc/intel/skylake/romstage/romstage.c index fda60875f2..0ec2f99e63 100644 --- a/src/soc/intel/skylake/romstage/romstage.c +++ b/src/soc/intel/skylake/romstage/romstage.c @@ -93,7 +93,7 @@ void soc_memory_init_params(struct romstage_params *params, upd->DdrFreqLimit = config->DdrFreqLimit; if (IS_ENABLED(CONFIG_SKIP_FSP_CAR)) { upd->FspCarBase = CONFIG_DCACHE_RAM_BASE; - upd->FspCarSize = CONFIG_DCACHE_RAM_SIZE_TOTAL; + upd->FspCarSize = CONFIG_DCACHE_RAM_SIZE; } } -- cgit v1.2.3