From d3476809955ffb69447cc02a5ea893ebd1da3eb3 Mon Sep 17 00:00:00 2001 From: Shaunak Saha Date: Sat, 8 Jul 2017 01:08:40 -0700 Subject: soc/intel/skylake: Add support in SKL for PMC common code Change-Id: I3742f9c22d990edd918713155ae0bb1853663b6f Signed-off-by: Shaunak Saha Reviewed-on: https://review.coreboot.org/20499 Reviewed-by: Aaron Durbin Tested-by: build bot (Jenkins) --- src/soc/intel/skylake/reset.c | 10 ++-------- 1 file changed, 2 insertions(+), 8 deletions(-) (limited to 'src/soc/intel/skylake/reset.c') diff --git a/src/soc/intel/skylake/reset.c b/src/soc/intel/skylake/reset.c index dee98a4c1e..d9e3ea5062 100644 --- a/src/soc/intel/skylake/reset.c +++ b/src/soc/intel/skylake/reset.c @@ -15,6 +15,7 @@ #include #include +#include #include #include #include @@ -22,19 +23,12 @@ static void do_force_global_reset(void) { - u32 reg32; - /*PMC Controller Device 0x1F, Func 02*/ - uint8_t *pmc_regs; - /* * BIOS should ensure it does a global reset * to reset both host and Intel ME by setting * PCH PMC [B0:D31:F2 register offset 0x1048 bit 20] */ - pmc_regs = pmc_mmio_regs(); - reg32 = read32(pmc_regs + ETR3); - reg32 |= ETR3_CF9GR; - write32(pmc_regs + ETR3, reg32); + pmc_global_reset_enable(true); /* Now BIOS can write 0x06 or 0x0E to 0xCF9 port * to global reset platform */ -- cgit v1.2.3