From f643b63c4dcd74c3de0c1d54de8b740d831d6d73 Mon Sep 17 00:00:00 2001 From: Angel Pons Date: Sat, 17 Apr 2021 12:55:59 +0200 Subject: soc/intel/skylake: Move pmc_set_disb() to pmutil.c MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit To drop bad __SIMPLE_DEVICE__ usage and for consistency with newer platforms, move pmc_set_disb() to pmutil.c and adapt it accordingly. Change-Id: I1a137b5b3120c350a04273567b9cb18c9a42a543 Signed-off-by: Angel Pons Reviewed-on: https://review.coreboot.org/c/coreboot/+/52463 Tested-by: build bot (Jenkins) Reviewed-by: Tim Wawrzynczak Reviewed-by: Michael Niewöhner --- src/soc/intel/skylake/pmutil.c | 14 ++++++++++++++ 1 file changed, 14 insertions(+) (limited to 'src/soc/intel/skylake/pmutil.c') diff --git a/src/soc/intel/skylake/pmutil.c b/src/soc/intel/skylake/pmutil.c index 115a9e58ec..35862c278b 100644 --- a/src/soc/intel/skylake/pmutil.c +++ b/src/soc/intel/skylake/pmutil.c @@ -113,6 +113,20 @@ const char *const *soc_std_gpe_sts_array(size_t *gpe_arr) return gpe_sts_bits; } +void pmc_set_disb(void) +{ + /* Set the DISB after DRAM init */ + u32 disb_val; + const pci_devfn_t dev = PCH_DEV_PMC; + + disb_val = pci_read_config32(dev, GEN_PMCON_A); + disb_val |= DISB; + + /* Don't clear bits that are write-1-to-clear */ + disb_val &= ~(GBL_RST_STS | MS4V); + pci_write_config32(dev, GEN_PMCON_A, disb_val); +} + uint8_t *pmc_mmio_regs(void) { uint32_t reg32; -- cgit v1.2.3