From c261c4b426ac806cca732bb30459f0e6e855828a Mon Sep 17 00:00:00 2001 From: Naresh G Solanki Date: Tue, 25 Apr 2017 12:09:07 +0530 Subject: soc/intel/skylake: Set xtal bypass on low power idle When using Wake On Voice &/or DCI, it requires xtal to be active during low power idle. With xtal being active in S0ix state power impact is 1-2 mW. Hence set xtal bypass bit in CIR31C for low power idle entry. TEST= Build with s0ix enable for Poppy. Boot to OS & verify that bit 22 of CIR31C register is set. s0ix works. Change-Id: Ide2d01536f652cd1b0ac32eede89ec410c5101cf Signed-off-by: Naresh G Solanki Reviewed-on: https://review.coreboot.org/19442 Tested-by: build bot (Jenkins) Reviewed-by: Aaron Durbin Reviewed-by: Furquan Shaikh --- src/soc/intel/skylake/include/soc/pmc.h | 3 ++- 1 file changed, 2 insertions(+), 1 deletion(-) (limited to 'src/soc/intel/skylake/include') diff --git a/src/soc/intel/skylake/include/soc/pmc.h b/src/soc/intel/skylake/include/soc/pmc.h index 10ea6ae894..4a80917fe4 100644 --- a/src/soc/intel/skylake/include/soc/pmc.h +++ b/src/soc/intel/skylake/include/soc/pmc.h @@ -98,5 +98,6 @@ #define GPE0_DW2_SHIFT 8 #define GBLRST_CAUSE0 0x124 #define GBLRST_CAUSE1 0x128 - +#define CIR31C 0x31c +#define XTALSDQDIS (1 << 22) #endif -- cgit v1.2.3