From 952cb03b9e08883da46fb57f99aec919f5a9b60a Mon Sep 17 00:00:00 2001 From: Rizwan Qureshi Date: Mon, 5 Oct 2015 19:11:39 +0530 Subject: intel/skylake: FSP 1.7.0 MemoryInit/SiliconInit params update In FSP 1.7.0 SataMode and SataEnable have been moved from MemoryInit to SiliconInit. Also, GpioTablePtr has been removed. USB phy settings added to SiliconInit, Enable the configs for USB equalization settings in coreboot. Addition of serialIO UPD to indicate FSP not to reinitialise UART2 controller during MemoryInit. BRANCH=none BUG=chrome-os-partner:45684, chrome-os-partner:42284, chrome-os-partner:41374 TEST=build for Kunimitsu, boot on FAB3, Also checked for Boot from USB, Boot from eMMC, USB Audio, Onboard Audio, Touch, Wifi, S3 entry/resume CQ-DEPEND=CL:*232947, CL:*232946, CL:*232948, CL:*232949 Change-Id: I2e8e6e32fc7074774ddcf1fb4c270bb56372b7df Signed-off-by: Patrick Georgi Original-Commit-Id: 623c5a52f3afedaf2c0bfe7361cfd627d093cb73 Original-Change-Id: I8b3be2c49893c564fe2197aa32bde6323bf425e9 Original-Signed-off-by: Rizwan Qureshi Original-Signed-off-by: Rishavnath Satapathy Original-Reviewed-on: https://chromium-review.googlesource.com/303661 Original-Reviewed-by: Aaron Durbin Reviewed-on: http://review.coreboot.org/12144 Tested-by: build bot (Jenkins) Reviewed-by: Patrick Georgi --- src/soc/intel/skylake/include/soc/serialio.h | 3 ++- 1 file changed, 2 insertions(+), 1 deletion(-) (limited to 'src/soc/intel/skylake/include') diff --git a/src/soc/intel/skylake/include/soc/serialio.h b/src/soc/intel/skylake/include/soc/serialio.h index 0bc07c30d7..9d85c45715 100644 --- a/src/soc/intel/skylake/include/soc/serialio.h +++ b/src/soc/intel/skylake/include/soc/serialio.h @@ -33,7 +33,8 @@ typedef enum { PchSerialIoAcpi, PchSerialIoPci, PchSerialIoAcpiHidden, - PchSerialIoLegacyUart + PchSerialIoLegacyUart, + PchSerialIoSkipInit } PCH_SERIAL_IO_MODE; typedef enum { -- cgit v1.2.3