From 7ef19036fbfeaad63ccb4dde26b3133d6128d0b8 Mon Sep 17 00:00:00 2001 From: Michael Niewöhner Date: Tue, 8 Oct 2019 00:30:38 +0200 Subject: soc/intel/skylake: move/rename files after drop of FSP 1.1 MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit Follow-up commit where only files are moved and paths adapted to make review of the previous commit easier. Change-Id: Iff1acbd286c2ba8e6613e866d4e2f893562e8973 Signed-off-by: Michael Niewöhner Signed-off-by: Matt DeVillier Reviewed-on: https://review.coreboot.org/c/coreboot/+/35868 Reviewed-by: Michael Niewöhner Reviewed-by: Nico Huber Tested-by: build bot (Jenkins) --- src/soc/intel/skylake/include/fsp20/soc/ramstage.h | 35 ---------------------- src/soc/intel/skylake/include/fsp20/soc/romstage.h | 32 -------------------- src/soc/intel/skylake/include/soc/ramstage.h | 35 ++++++++++++++++++++++ src/soc/intel/skylake/include/soc/romstage.h | 32 ++++++++++++++++++++ 4 files changed, 67 insertions(+), 67 deletions(-) delete mode 100644 src/soc/intel/skylake/include/fsp20/soc/ramstage.h delete mode 100644 src/soc/intel/skylake/include/fsp20/soc/romstage.h create mode 100644 src/soc/intel/skylake/include/soc/ramstage.h create mode 100644 src/soc/intel/skylake/include/soc/romstage.h (limited to 'src/soc/intel/skylake/include') diff --git a/src/soc/intel/skylake/include/fsp20/soc/ramstage.h b/src/soc/intel/skylake/include/fsp20/soc/ramstage.h deleted file mode 100644 index e5660a6f66..0000000000 --- a/src/soc/intel/skylake/include/fsp20/soc/ramstage.h +++ /dev/null @@ -1,35 +0,0 @@ -/* - * This file is part of the coreboot project. - * - * Copyright (C) 2014 Google Inc. - * Copyright (C) 2015-2017 Intel Corporation. - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ - -#ifndef _SOC_RAMSTAGE_H_ -#define _SOC_RAMSTAGE_H_ - -#include -#include -#include - -#include "../../../chip.h" - -#define FSP_SIL_UPD FSP_S_CONFIG -#define FSP_MEM_UPD FSP_M_CONFIG - -void mainboard_silicon_init_params(FSP_S_CONFIG *params); -void soc_fsp_load(void); -void soc_init_pre_device(void *chip_info); -void soc_irq_settings(FSP_SIL_UPD *params); -const char *soc_acpi_name(const struct device *dev); - -#endif diff --git a/src/soc/intel/skylake/include/fsp20/soc/romstage.h b/src/soc/intel/skylake/include/fsp20/soc/romstage.h deleted file mode 100644 index 364bf52529..0000000000 --- a/src/soc/intel/skylake/include/fsp20/soc/romstage.h +++ /dev/null @@ -1,32 +0,0 @@ -/* - * This file is part of the coreboot project. - * - * Copyright (C) 2014 Google Inc. - * Copyright (C) 2015-2016 Intel Corporation. - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ - -#ifndef _SOC_ROMSTAGE_H_ -#define _SOC_ROMSTAGE_H_ - -#include - -void mainboard_memory_init_params(FSPM_UPD *mupd); -void systemagent_early_init(void); -int smbus_read_byte(unsigned int device, unsigned int address); -/* Board type */ -enum board_type { - BOARD_TYPE_MOBILE = 0, - BOARD_TYPE_DESKTOP = 1, - BOARD_TYPE_ULT_ULX = 5, - BOARD_TYPE_SERVER = 7 -}; -#endif /* _SOC_ROMSTAGE_H_ */ diff --git a/src/soc/intel/skylake/include/soc/ramstage.h b/src/soc/intel/skylake/include/soc/ramstage.h new file mode 100644 index 0000000000..4157c4e09b --- /dev/null +++ b/src/soc/intel/skylake/include/soc/ramstage.h @@ -0,0 +1,35 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2014 Google Inc. + * Copyright (C) 2015-2017 Intel Corporation. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#ifndef _SOC_RAMSTAGE_H_ +#define _SOC_RAMSTAGE_H_ + +#include +#include +#include + +#include "../../chip.h" + +#define FSP_SIL_UPD FSP_S_CONFIG +#define FSP_MEM_UPD FSP_M_CONFIG + +void mainboard_silicon_init_params(FSP_S_CONFIG *params); +void soc_fsp_load(void); +void soc_init_pre_device(void *chip_info); +void soc_irq_settings(FSP_SIL_UPD *params); +const char *soc_acpi_name(const struct device *dev); + +#endif diff --git a/src/soc/intel/skylake/include/soc/romstage.h b/src/soc/intel/skylake/include/soc/romstage.h new file mode 100644 index 0000000000..364bf52529 --- /dev/null +++ b/src/soc/intel/skylake/include/soc/romstage.h @@ -0,0 +1,32 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2014 Google Inc. + * Copyright (C) 2015-2016 Intel Corporation. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#ifndef _SOC_ROMSTAGE_H_ +#define _SOC_ROMSTAGE_H_ + +#include + +void mainboard_memory_init_params(FSPM_UPD *mupd); +void systemagent_early_init(void); +int smbus_read_byte(unsigned int device, unsigned int address); +/* Board type */ +enum board_type { + BOARD_TYPE_MOBILE = 0, + BOARD_TYPE_DESKTOP = 1, + BOARD_TYPE_ULT_ULX = 5, + BOARD_TYPE_SERVER = 7 +}; +#endif /* _SOC_ROMSTAGE_H_ */ -- cgit v1.2.3