From 7e9cb9281581fdf1b75ef5e6f32a1ec322e11c8f Mon Sep 17 00:00:00 2001 From: Subrata Banik Date: Thu, 17 Aug 2017 14:07:35 +0530 Subject: soc/intel/skylake: Add support for all UART port index Select LPSS UART Base address based on LPSS UART port index. Change-Id: I306d3d299f8d6a890ae519c74008f9d0d9dd1a76 Signed-off-by: Subrata Banik Reviewed-on: https://review.coreboot.org/20997 Tested-by: build bot (Jenkins) Reviewed-by: Aaron Durbin --- src/soc/intel/skylake/include/soc/iomap.h | 7 +++++-- 1 file changed, 5 insertions(+), 2 deletions(-) (limited to 'src/soc/intel/skylake/include') diff --git a/src/soc/intel/skylake/include/soc/iomap.h b/src/soc/intel/skylake/include/soc/iomap.h index 52ef64041e..ff4e4b0396 100644 --- a/src/soc/intel/skylake/include/soc/iomap.h +++ b/src/soc/intel/skylake/include/soc/iomap.h @@ -23,8 +23,11 @@ #define MCFG_BASE_ADDRESS CONFIG_MMCONF_BASE_ADDRESS #define MCFG_BASE_SIZE 0x4000000 -#define UART_DEBUG_BASE_ADDRESS 0xfe034000 -#define UART_DEBUG_BASE_SIZE 0x1000 +#define UART_DEBUG_BASE_0_SIZE 0x1000 +#define UART_BASE_0_ADDRESS 0xfe030000 +/* Both UART BAR 0 and 1 are 4KB in size */ +#define UART_BASE_0_ADDR(x) (UART_BASE_0_ADDRESS + (2 * \ + UART_DEBUG_BASE_0_SIZE * (x))) #define EARLY_I2C_BASE_ADDRESS 0xfe040000 #define EARLY_I2C_BASE(x) (EARLY_I2C_BASE_ADDRESS + (0x1000 * (x))) -- cgit v1.2.3