From 6a00113de8b9060a7227bcfa79b3786e3e592a33 Mon Sep 17 00:00:00 2001 From: Stefan Reinauer Date: Thu, 13 Jul 2017 02:20:27 +0200 Subject: Rename __attribute__((packed)) --> __packed Also unify __attribute__ ((..)) to __attribute__((..)) and handle ((__packed__)) like ((packed)) Change-Id: Ie60a51c3fa92b5009724a5b7c2932e361bf3490c Signed-off-by: Stefan Reinauer Reviewed-on: https://review.coreboot.org/15921 Tested-by: build bot (Jenkins) Reviewed-by: Aaron Durbin --- src/soc/intel/skylake/include/soc/device_nvs.h | 3 ++- src/soc/intel/skylake/include/soc/me.h | 16 +++++++++------- src/soc/intel/skylake/include/soc/nvs.h | 3 ++- src/soc/intel/skylake/include/soc/pei_data.h | 3 ++- src/soc/intel/skylake/include/soc/pm.h | 3 ++- src/soc/intel/skylake/include/soc/smm.h | 3 ++- 6 files changed, 19 insertions(+), 12 deletions(-) (limited to 'src/soc/intel/skylake/include') diff --git a/src/soc/intel/skylake/include/soc/device_nvs.h b/src/soc/intel/skylake/include/soc/device_nvs.h index 79b516d9b5..02c9e65809 100644 --- a/src/soc/intel/skylake/include/soc/device_nvs.h +++ b/src/soc/intel/skylake/include/soc/device_nvs.h @@ -18,6 +18,7 @@ #define _SOC_DEVICE_NVS_H_ #include +#include /* Offset in Global NVS where this structure lives */ #define DEVICE_NVS_OFFSET 0x1000 @@ -38,6 +39,6 @@ typedef struct { u8 enable[11]; u32 bar0[11]; u32 bar1[11]; -} __attribute__((packed)) device_nvs_t; +} __packed device_nvs_t; #endif diff --git a/src/soc/intel/skylake/include/soc/me.h b/src/soc/intel/skylake/include/soc/me.h index 2736d1a04f..e88711ddf3 100644 --- a/src/soc/intel/skylake/include/soc/me.h +++ b/src/soc/intel/skylake/include/soc/me.h @@ -18,6 +18,8 @@ #ifndef _SKYLAKE_ME_H_ #define _SKYLAKE_ME_H_ +#include + /* * Management Engine PCI registers */ @@ -68,7 +70,7 @@ union me_hfs { u32 current_power_source: 2; u32 d3_support_valid: 1; u32 d0i3_support_valid: 1; - } __attribute__ ((packed)) fields; + } __packed fields; }; #define PCI_ME_HFSTS2 0x48 @@ -166,7 +168,7 @@ union me_hfs2 { u32 current_state: 8; u32 current_pmevent: 4; u32 progress_code: 4; - } __attribute__ ((packed)) fields; + } __packed fields; }; #define PCI_ME_HFSTS3 0x60 @@ -183,7 +185,7 @@ union me_hfs3 { u32 reserved2: 21; u32 encrypt_key_override: 1; u32 power_down_mitigation: 1; - } __attribute__ ((packed)) fields; + } __packed fields; }; #define PCI_ME_HFSTS6 0x6c @@ -195,7 +197,7 @@ union me_hfs6 { struct { u32 reserved1: 30; u32 fpf_nvars: 2; - } __attribute__ ((packed)) fields; + } __packed fields; }; /* @@ -216,7 +218,7 @@ union host_csr { u32 host_read_offset: 8; u32 host_write_offset: 8; u32 me_cir_depth: 8; - } __attribute__ ((packed)) fields; + } __packed fields; }; #define MMIO_ME_CB_RW 0x08 @@ -234,7 +236,7 @@ union me_csr { u32 me_read_offset: 8; u32 me_write_offset: 8; u32 me_cir_buff: 8; - } __attribute__ ((packed)) fields; + } __packed fields; }; #define MMIO_ME_D0I3 0x800 @@ -265,7 +267,7 @@ union mei_header { u32 length: 9; u32 reserved: 6; u32 is_complete: 1; - } __attribute__ ((packed)) fields; + } __packed fields; }; void intel_me_status(void); diff --git a/src/soc/intel/skylake/include/soc/nvs.h b/src/soc/intel/skylake/include/soc/nvs.h index f72616f05e..4ca3d227b0 100644 --- a/src/soc/intel/skylake/include/soc/nvs.h +++ b/src/soc/intel/skylake/include/soc/nvs.h @@ -19,6 +19,7 @@ #define _SOC_NVS_H_ #include +#include #include typedef struct { @@ -60,7 +61,7 @@ typedef struct { /* ChromeOS specific (0x100 - 0xfff) */ chromeos_acpi_t chromeos; -} __attribute__((packed)) global_nvs_t; +} __packed global_nvs_t; #if ENV_SMM /* Used in SMM to find the ACPI GNVS address */ diff --git a/src/soc/intel/skylake/include/soc/pei_data.h b/src/soc/intel/skylake/include/soc/pei_data.h index be8ba79b92..58485837c6 100644 --- a/src/soc/intel/skylake/include/soc/pei_data.h +++ b/src/soc/intel/skylake/include/soc/pei_data.h @@ -31,6 +31,7 @@ #define _PEI_DATA_H_ #include +#include #define PEI_VERSION 22 @@ -92,7 +93,7 @@ struct pei_data { void *data_to_save; int data_to_save_size; int mem_cfg_id; -} __attribute__((packed)); +} __packed; typedef struct pei_data PEI_DATA; diff --git a/src/soc/intel/skylake/include/soc/pm.h b/src/soc/intel/skylake/include/soc/pm.h index 15c291cc96..67b1f438b6 100644 --- a/src/soc/intel/skylake/include/soc/pm.h +++ b/src/soc/intel/skylake/include/soc/pm.h @@ -17,6 +17,7 @@ #ifndef _SOC_PM_H_ #define _SOC_PM_H_ +#include #include #include #include @@ -147,7 +148,7 @@ struct chipset_power_state { uint32_t gen_pmcon_b; uint32_t gblrst_cause[2]; uint32_t prev_sleep_state; -} __attribute__ ((packed)); +} __packed; struct chipset_power_state *fill_power_state(void); diff --git a/src/soc/intel/skylake/include/soc/smm.h b/src/soc/intel/skylake/include/soc/smm.h index 6ba6fdb72c..06c4aacd3d 100644 --- a/src/soc/intel/skylake/include/soc/smm.h +++ b/src/soc/intel/skylake/include/soc/smm.h @@ -18,6 +18,7 @@ #define _SOC_SMM_H_ #include +#include #include #include #include @@ -26,7 +27,7 @@ struct ied_header { char signature[10]; u32 size; u8 reserved[34]; -} __attribute__ ((packed)); +} __packed; struct smm_relocation_params { u32 smram_base; -- cgit v1.2.3