From 56715ec23f6c34ae4bda3ac197aba0d90af06660 Mon Sep 17 00:00:00 2001 From: Usha P Date: Fri, 8 Nov 2019 16:00:40 +0530 Subject: soc/intel/skylake: Refactor pch_early_init() code This patch keeps required pch_early_init() function like ABASE programming, GPE and RTC init into bootblock and moves remaining functions like TCO configuration and SMBUS init into romstage/pch.c in order to maintain only required chipset programming for bootblock and verstage. TEST=Able to build and boot soraka. Change-Id: Idf7b04edc3fce147f7857591ce7d5a0cd03f43fe Signed-off-by: Usha P Reviewed-on: https://review.coreboot.org/c/coreboot/+/36672 Tested-by: build bot (Jenkins) Reviewed-by: Subrata Banik --- src/soc/intel/skylake/include/soc/bootblock.h | 2 +- src/soc/intel/skylake/include/soc/romstage.h | 1 + 2 files changed, 2 insertions(+), 1 deletion(-) (limited to 'src/soc/intel/skylake/include') diff --git a/src/soc/intel/skylake/include/soc/bootblock.h b/src/soc/intel/skylake/include/soc/bootblock.h index a40f439936..302db50fb3 100644 --- a/src/soc/intel/skylake/include/soc/bootblock.h +++ b/src/soc/intel/skylake/include/soc/bootblock.h @@ -24,7 +24,7 @@ void bootblock_pch_early_init(void); /* Bootblock post console init programming */ void i2c_early_init(void); -void pch_early_init(void); +void pch_init(void); void pch_early_iorange_init(void); void report_platform_info(void); void report_memory_config(void); diff --git a/src/soc/intel/skylake/include/soc/romstage.h b/src/soc/intel/skylake/include/soc/romstage.h index 364bf52529..674652625b 100644 --- a/src/soc/intel/skylake/include/soc/romstage.h +++ b/src/soc/intel/skylake/include/soc/romstage.h @@ -21,6 +21,7 @@ void mainboard_memory_init_params(FSPM_UPD *mupd); void systemagent_early_init(void); +void pch_init(void); int smbus_read_byte(unsigned int device, unsigned int address); /* Board type */ enum board_type { -- cgit v1.2.3