From 20c3ea5c4f2c83df7c9416b2b9cbcff63e2c74f1 Mon Sep 17 00:00:00 2001
From: Shelley Chen <shchen@chromium.org>
Date: Thu, 29 Jun 2017 11:31:16 -0700
Subject: soc/intel/skylake: Set PsysPL2 MSR

BUG=b:7473486, b:35775024
BRANCH=None
TEST=On bootup make sure PL2 and PsysPL2 values set
     properly (through debug output)

Change-Id: I847a8458382e7db1689b426f32ff2dcbc5a0899c
Signed-off-by: Shelley Chen <shchen@chromium.org>
Reviewed-on: https://review.coreboot.org/20418
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-by: Furquan Shaikh <furquan@google.com>
---
 src/soc/intel/skylake/include/soc/msr.h | 1 +
 1 file changed, 1 insertion(+)

(limited to 'src/soc/intel/skylake/include')

diff --git a/src/soc/intel/skylake/include/soc/msr.h b/src/soc/intel/skylake/include/soc/msr.h
index 81b6cc9de1..4ff4ad2d49 100644
--- a/src/soc/intel/skylake/include/soc/msr.h
+++ b/src/soc/intel/skylake/include/soc/msr.h
@@ -37,5 +37,6 @@
 #define MSR_VR_MISC_CONFIG2		0x636
 #define MSR_PP0_POWER_LIMIT		0x638
 #define MSR_PP1_POWER_LIMIT		0x640
+#define MSR_PLATFORM_POWER_LIMIT        0x65c
 
 #endif
-- 
cgit v1.2.3