From a2d4062d427d18127707306dada5e79d69bd3691 Mon Sep 17 00:00:00 2001
From: Naresh G Solanki <naresh.solanki@intel.com>
Date: Tue, 30 Aug 2016 20:47:13 +0530
Subject: soc/intel/skylake: Add FSP 2.0 support in ramstage

Add FSP 2.0 support in ramstage.
Populate required Fsp Silicon Init params and configure mainboard
specific GPIOs.
Define function fsp_soc_get_igd_bar needed by fsp2.0 driver for
pre OS screens.

Change-Id: Ib38ca7547b5d5ec2b268698b8886d5caa28d6497
Signed-off-by: Rizwan Qureshi <rizwan.qureshi@intel.com>
Signed-off-by: Naresh G Solanki <naresh.solanki@intel.com>
Reviewed-on: https://review.coreboot.org/16592
Tested-by: build bot (Jenkins)
Reviewed-by: Duncan Laurie <dlaurie@chromium.org>
---
 src/soc/intel/skylake/igd.c | 10 ++++++++--
 1 file changed, 8 insertions(+), 2 deletions(-)

(limited to 'src/soc/intel/skylake/igd.c')

diff --git a/src/soc/intel/skylake/igd.c b/src/soc/intel/skylake/igd.c
index 93f05cc150..1cc30ad8f4 100644
--- a/src/soc/intel/skylake/igd.c
+++ b/src/soc/intel/skylake/igd.c
@@ -24,6 +24,7 @@
 #include <device/pci.h>
 #include <device/pci_ids.h>
 #include <drivers/intel/gma/i915_reg.h>
+#include <fsp/util.h>
 #include <soc/acpi.h>
 #include <soc/cpu.h>
 #include <soc/pm.h>
@@ -33,6 +34,11 @@
 #include <string.h>
 #include <vboot/vbnv.h>
 
+uintptr_t fsp_soc_get_igd_bar(void)
+{
+	return find_resource(SA_DEV_IGD, PCI_BASE_ADDRESS_2)->base;
+}
+
 u32 map_oprom_vendev(u32 vendev)
 {
 	return SA_IGD_OPROM_VENDEV;
@@ -79,7 +85,7 @@ static void igd_init(struct device *dev)
 		gtt_write(DDI_BUF_CTL_A, ddi_buf_ctl);
 	}
 
-	if (IS_ENABLED(CONFIG_GOP_SUPPORT))
+	if (IS_ENABLED(CONFIG_ADD_VBT_DATA_FILE))
 		return;
 
 	/* IGD needs to be Bus Master */
@@ -153,7 +159,7 @@ static unsigned long write_acpi_igd_opregion(device_t device,
 	igd_opregion_t *opregion;
 
 	/* If GOP is not used, exit here */
-	if (!IS_ENABLED(CONFIG_GOP_SUPPORT))
+	if (!IS_ENABLED(CONFIG_ADD_VBT_DATA_FILE))
 		return current;
 
 	/* If IGD is disabled, exit here */
-- 
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