From 6a740539d1005eb14d21da40d7d14ff7250da508 Mon Sep 17 00:00:00 2001
From: Li Cheng Sooi
Date: Wed, 4 Jan 2017 09:48:39 +0800
Subject: soc/intel/skylake: Add SKL SOC PCH H GPIO support
Add SKL/KBL PCH-H GPIO settings referring from SKL PCH-H
specifications to support sklrvp11.
Split the gpio_defs.h into headers gpio_pch_h_defs.h and
gpio_soc_defs.h for PCH-H specific and SOC specific GPIO
defs respectively.
Change-Id: I5eaf8d809a1244a56038cbfc29502910eb90f9f2
Signed-off-by: Li Cheng Sooi
Signed-off-by: Rahul Kumar Gupta
Reviewed-on: https://review.coreboot.org/18027
Tested-by: build bot (Jenkins)
Reviewed-by: Aaron Durbin
---
src/soc/intel/skylake/gpio.c | 13 +++++++++++++
1 file changed, 13 insertions(+)
(limited to 'src/soc/intel/skylake/gpio.c')
diff --git a/src/soc/intel/skylake/gpio.c b/src/soc/intel/skylake/gpio.c
index 6334b3e9bd..f65b1c98cd 100644
--- a/src/soc/intel/skylake/gpio.c
+++ b/src/soc/intel/skylake/gpio.c
@@ -45,12 +45,21 @@ static const struct gpio_community communities[] = {
{
.port_id = PID_GPIOCOM1,
.min = GPP_C0,
+#if IS_ENABLED(CONFIG_SKYLAKE_SOC_PCH_H)
+ .max = GPP_H23,
+#else
.max = GPP_E23,
+#endif
},
{
.port_id = PID_GPIOCOM3,
+#if IS_ENABLED(CONFIG_SKYLAKE_SOC_PCH_H)
+ .min = GPP_I0,
+ .max = GPP_I10,
+#else
.min = GPP_F0,
.max = GPP_G7,
+#endif
},
{
.port_id = PID_GPIOCOM2,
@@ -67,6 +76,10 @@ static const char *gpio_group_names[GPIO_NUM_GROUPS] = {
"GPP_E",
"GPP_F",
"GPP_G",
+#if IS_ENABLED(CONFIG_SKYLAKE_SOC_PCH_H)
+ "GPP_H",
+ "GPP_I",
+#endif
"GPD",
};
--
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