From ccd174686ea4f5b814486fd10e55d879c1f07bdc Mon Sep 17 00:00:00 2001 From: Praveen hodagatta pranesh Date: Sat, 3 Nov 2018 01:49:15 +0800 Subject: soc/intel/skylake: Add FSP CAR support for kabylake Kabylake RVP11 uses FSPT to support Intel security features like bootguard verify boot and measured boot. This patch add FSP CAR support for kabylake by programming tempraminit parameters in fspcar.c and also add FSP_T_XIP default if FSP_CAR is selected in order to relocate FSPT binary while adding it in CBFS so that it can be executed in place. BUG=None TEST=Build and Boot to UEFI payload on kabylake RVP11 board and verified for successful FSP CAR setup. Change-Id: Id180ff9191d734c581ba7bf3879eaa730a799b52 Signed-off-by: Praveen hodagatta pranesh Reviewed-on: https://review.coreboot.org/29433 Tested-by: build bot (Jenkins) Reviewed-by: Boon Tiong Teo Reviewed-by: Aaron Durbin Reviewed-by: Furquan Shaikh --- src/soc/intel/skylake/fspcar.c | 34 ++++++++++++++++++++++++++++++++++ 1 file changed, 34 insertions(+) create mode 100644 src/soc/intel/skylake/fspcar.c (limited to 'src/soc/intel/skylake/fspcar.c') diff --git a/src/soc/intel/skylake/fspcar.c b/src/soc/intel/skylake/fspcar.c new file mode 100644 index 0000000000..a4c3726492 --- /dev/null +++ b/src/soc/intel/skylake/fspcar.c @@ -0,0 +1,34 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2018 Intel Corp. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ +#include +#include + +const FSPT_UPD temp_ram_init_params = { + .FspUpdHeader = { + .Signature = 0x545F4450554C424B, /* 'KBLUPD_T' */ + .Revision = 1, + .Reserved = {0}, + }, + .FsptCoreUpd = { + .MicrocodeRegionBase = + (uint32_t)CONFIG_CPU_MICROCODE_CBFS_LOC, + .MicrocodeRegionSize = + (uint32_t)CONFIG_CPU_MICROCODE_CBFS_LEN, + .CodeRegionBase = + (uint32_t)(0x100000000ULL - CONFIG_ROM_SIZE), + .CodeRegionSize = (uint32_t)CONFIG_ROM_SIZE, + }, +}; -- cgit v1.2.3