From c204aaa23b8455457920a56a85b0128f9818f461 Mon Sep 17 00:00:00 2001 From: Subrata Banik Date: Thu, 17 Aug 2017 15:49:58 +0530 Subject: soc/intel/skylake: Add LPC and SPI lock down config option This patch to provide new config options to perform LPC and SPI lock down either by FSP or coreboot. Remove EISS bit programming as well. TEST=Build and boot Eve and Poppy. Change-Id: If174915b4d0c581f36b54b2b8cd970a93c6454bc Signed-off-by: Subrata Banik Reviewed-on: https://review.coreboot.org/21068 Tested-by: build bot (Jenkins) Reviewed-by: Aaron Durbin --- src/soc/intel/skylake/finalize.c | 20 +++----------------- 1 file changed, 3 insertions(+), 17 deletions(-) (limited to 'src/soc/intel/skylake/finalize.c') diff --git a/src/soc/intel/skylake/finalize.c b/src/soc/intel/skylake/finalize.c index 9759382149..404d217a87 100644 --- a/src/soc/intel/skylake/finalize.c +++ b/src/soc/intel/skylake/finalize.c @@ -184,8 +184,8 @@ static void soc_lockdown(void) pci_write_config8(dev, GEN_PMCON_A, reg8); } - /* Bios Interface Lock */ - if (config->LockDownConfigBiosInterface == 0) { + if (config->chipset_lockdown == CHIPSET_LOCKDOWN_COREBOOT) { + /* Bios Interface Lock */ pci_write_config8(PCH_DEV_LPC, BIOS_CNTL, pci_read_config8(PCH_DEV_LPC, BIOS_CNTL) | LPC_BC_BILD); @@ -196,10 +196,8 @@ static void soc_lockdown(void) /* GCS reg of DMI */ pcr_or8(PID_DMI, PCR_DMI_GCS, PCR_DMI_GCS_BILD); - } - /* Bios Lock */ - if (config->LockDownConfigBiosLock == 0) { + /* Bios Lock */ pci_write_config8(PCH_DEV_LPC, BIOS_CNTL, pci_read_config8(PCH_DEV_LPC, BIOS_CNTL) | LPC_BC_LE); @@ -209,18 +207,6 @@ static void soc_lockdown(void) fast_spi_set_lock_enable(); } - - /* SPIEiss */ - if (config->LockDownConfigSpiEiss == 0) { - pci_write_config8(PCH_DEV_LPC, BIOS_CNTL, - pci_read_config8(PCH_DEV_LPC, - BIOS_CNTL) | LPC_BC_EISS); - - /* Ensure an additional read back after performing lock down */ - pci_read_config8(PCH_DEV_LPC, BIOS_CNTL); - - fast_spi_set_eiss(); - } } static void soc_finalize(void *unused) -- cgit v1.2.3