From fc36e9fb0e81cf7b6b17a51f023d030b0ab117f9 Mon Sep 17 00:00:00 2001 From: Patrick Rudolph Date: Mon, 25 Jan 2021 10:46:16 +0100 Subject: soc/intel/*: Move prmrr_core_configure MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit Move prmrr_core_configure before clearing MCEs. This is required for the following patch in order to update microcode after PRMRR has been configured, but before MCEs have been cleared. According to Document 565432 this should be no issue in regards to SGX activation. Change-Id: Id2808a3989adff493aaf4175cbeccd080efaaedf Signed-off-by: Patrick Rudolph Reviewed-on: https://review.coreboot.org/c/coreboot/+/49898 Tested-by: build bot (Jenkins) Reviewed-by: Michael Niewöhner Reviewed-by: Tim Wawrzynczak Reviewed-by: Angel Pons --- src/soc/intel/skylake/cpu.c | 8 ++++---- 1 file changed, 4 insertions(+), 4 deletions(-) (limited to 'src/soc/intel/skylake/cpu.c') diff --git a/src/soc/intel/skylake/cpu.c b/src/soc/intel/skylake/cpu.c index 1647db4855..307c849550 100644 --- a/src/soc/intel/skylake/cpu.c +++ b/src/soc/intel/skylake/cpu.c @@ -97,6 +97,10 @@ static void configure_c_states(void) /* All CPUs including BSP will run the following function. */ void soc_core_init(struct device *cpu) { + /* Configure Core PRMRR for SGX. */ + if (CONFIG(SOC_INTEL_COMMON_BLOCK_SGX_ENABLE)) + prmrr_core_configure(); + /* Clear out pending MCEs */ /* TODO(adurbin): This should only be done on a cold boot. Also, some * of these banks are core vs package scope. For now every CPU clears @@ -126,10 +130,6 @@ void soc_core_init(struct device *cpu) /* Enable Turbo */ enable_turbo(); - - /* Configure Core PRMRR for SGX. */ - if (CONFIG(SOC_INTEL_COMMON_BLOCK_SGX_ENABLE)) - prmrr_core_configure(); } static void per_cpu_smm_trigger(void) -- cgit v1.2.3