From e18e6427d0f3261f9ec361d4418b8fe1dd7cc469 Mon Sep 17 00:00:00 2001 From: Martin Roth Date: Sat, 3 Jun 2017 20:03:18 -0600 Subject: src: change coreboot to lowercase MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit The word 'coreboot' should always be written in lowercase, even at the start of a sentence. Change-Id: I7945ddb988262e7483da4e623cedf972380e65a2 Signed-off-by: Martin Roth Reviewed-on: https://review.coreboot.org/20029 Tested-by: build bot (Jenkins) Reviewed-by: Philippe Mathieu-Daudé Reviewed-by: Patrick Georgi --- src/soc/intel/skylake/cpu.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) (limited to 'src/soc/intel/skylake/cpu.c') diff --git a/src/soc/intel/skylake/cpu.c b/src/soc/intel/skylake/cpu.c index 95d9ad9c8c..dddc1c3c7e 100644 --- a/src/soc/intel/skylake/cpu.c +++ b/src/soc/intel/skylake/cpu.c @@ -226,7 +226,7 @@ static void configure_isst(void) if (conf->speed_shift_enable) { /* * Kernel driver checks CPUID.06h:EAX[Bit 7] to determine if HWP - is supported or not. Coreboot needs to configure MSR 0x1AA + is supported or not. coreboot needs to configure MSR 0x1AA which is then reflected in the CPUID register. */ msr = rdmsr(MSR_MISC_PWR_MGMT); -- cgit v1.2.3