From b54d15487ace81af9e3a1f9f64a509624bb5081d Mon Sep 17 00:00:00 2001 From: Wei Shun Chang Date: Mon, 9 Apr 2018 11:46:43 +0800 Subject: soc/intel/skylake: Support PL1 override option In legacy mode, DPTF on some systems may rely on MMIO to control PL1 settings. However, MSR PL1 also contributes to the decision of max PL1 power; and in the current design, the lower value takes effect. In order to align MMIO and MSR settings, a tdp_pl1_override option is added to override the MSR PL1 limitation. BRANCH=eve BUG=b:73133864 TEST=1. Write PL1 override setting in devicetree.cb 2. Verify the MSR PL1 limitation is set correctly. Change-Id: I35b8747ad3ee4c68c30d49a9436aa319360bab9b Signed-off-by: Lucas Chen Reviewed-on: https://review.coreboot.org/28079 Tested-by: build bot (Jenkins) Reviewed-by: Duncan Laurie Reviewed-by: Furquan Shaikh --- src/soc/intel/skylake/cpu.c | 6 ++++-- 1 file changed, 4 insertions(+), 2 deletions(-) (limited to 'src/soc/intel/skylake/cpu.c') diff --git a/src/soc/intel/skylake/cpu.c b/src/soc/intel/skylake/cpu.c index 5535ec641d..417c4bcdb1 100644 --- a/src/soc/intel/skylake/cpu.c +++ b/src/soc/intel/skylake/cpu.c @@ -117,7 +117,7 @@ void set_power_limits(u8 power_limit_1_time) msr_t msr = rdmsr(MSR_PLATFORM_INFO); msr_t limit; unsigned int power_unit; - unsigned int tdp, min_power, max_power, max_time, tdp_pl2; + unsigned int tdp, min_power, max_power, max_time, tdp_pl2, tdp_pl1; u8 power_limit_1_val; struct device *dev = SA_DEV_ROOT; config_t *conf = dev->chip_info; @@ -154,7 +154,9 @@ void set_power_limits(u8 power_limit_1_time) /* Set long term power limit to TDP */ limit.lo = 0; - limit.lo |= tdp & PKG_POWER_LIMIT_MASK; + tdp_pl1 = ((conf->tdp_pl1_override == 0) ? + tdp : (conf->tdp_pl1_override * power_unit)); + limit.lo |= (tdp_pl1 & PKG_POWER_LIMIT_MASK); /* Set PL1 Pkg Power clamp bit */ limit.lo |= PKG_POWER_LIMIT_CLAMP; -- cgit v1.2.3