From 6dd4f76c77af8b12a7dc5d617b9c72f63ea1352f Mon Sep 17 00:00:00 2001 From: Matt DeVillier Date: Fri, 2 Mar 2018 14:22:14 -0500 Subject: soc/skylake/cpu: Fix Intel SpeedStep enable/disable In an attempt at consolidation, commit 0a203d1 [1] introduced an additional read/write of the MISC_ENABLE msr, as well a bug which nullified the setting of Intel SpeedStep by inserting said read/write calls in between another set of read/write calls to the same msr. Fix by reverting to previous (simpler) implementation. [1] soc/intel/skylake: Use CPU common library code https://review.coreboot.org/19566 Test: boot Linux on Librem13v2, read MISC_ENABLE msr and verify SpeedStep bit correctly set based on devicetree setting. Change-Id: Id2ac660bf8ea56d45e8c3f631a586b74106a6cc9 Signed-off-by: Youness Alaoui Signed-off-by: Matt DeVillier Reviewed-on: https://review.coreboot.org/25330 Tested-by: build bot (Jenkins) Reviewed-by: Aaron Durbin --- src/soc/intel/skylake/cpu.c | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) (limited to 'src/soc/intel/skylake/cpu.c') diff --git a/src/soc/intel/skylake/cpu.c b/src/soc/intel/skylake/cpu.c index 6e98afaffd..1a2de73f8d 100644 --- a/src/soc/intel/skylake/cpu.c +++ b/src/soc/intel/skylake/cpu.c @@ -293,9 +293,9 @@ static void configure_misc(void) msr.lo |= (1 << 0); /* Fast String enable */ msr.lo |= (1 << 3); /* TM1/TM2/EMTTM enable */ if (conf->eist_enable) - cpu_enable_eist(); + msr.lo |= (1 << 16); /* Enhanced SpeedStep Enable */ else - cpu_disable_eist(); + msr.lo &= ~(1 << 16); /* Enhanced SpeedStep Disable */ wrmsr(IA32_MISC_ENABLE, msr); /* Disable Thermal interrupts */ -- cgit v1.2.3