From 6b45ee44a9bbccb4dc42ea454aa20ef7d02a9fd1 Mon Sep 17 00:00:00 2001 From: Subrata Banik Date: Fri, 12 May 2017 11:43:57 +0530 Subject: soc/intel/skylake: Add option to enable/disable EIST Set MSR 0x1A0 bit[16] based on EIST config option. Default Hardware Managed P-state (HWP) also known as Intel Speed Shift is enabled on SKL hence disable EIST and ACPI P-state table. Change-Id: I2b7374a8a04b596edcc88165b64980b7aa09e2a7 Signed-off-by: Subrata Banik Reviewed-on: https://review.coreboot.org/19676 Tested-by: build bot (Jenkins) Reviewed-by: Aaron Durbin Reviewed-by: Paul Menzel --- src/soc/intel/skylake/cpu.c | 7 ++++++- 1 file changed, 6 insertions(+), 1 deletion(-) (limited to 'src/soc/intel/skylake/cpu.c') diff --git a/src/soc/intel/skylake/cpu.c b/src/soc/intel/skylake/cpu.c index c472617b0f..057241327b 100644 --- a/src/soc/intel/skylake/cpu.c +++ b/src/soc/intel/skylake/cpu.c @@ -245,12 +245,17 @@ static void configure_isst(void) static void configure_misc(void) { + device_t dev = SA_DEV_ROOT; + config_t *conf = dev->chip_info; msr_t msr; msr = rdmsr(IA32_MISC_ENABLE); msr.lo |= (1 << 0); /* Fast String enable */ msr.lo |= (1 << 3); /* TM1/TM2/EMTTM enable */ - msr.lo |= (1 << 16); /* Enhanced SpeedStep Enable */ + if (conf->eist_enable) + msr.lo |= (1 << 16); /* Enhanced SpeedStep Enable */ + else + msr.lo &= ~(1 << 16); /* Enhanced SpeedStep Disable */ wrmsr(IA32_MISC_ENABLE, msr); /* Disable Thermal interrupts */ -- cgit v1.2.3