From 07cbd7684f13b90fc2862e8f32a2200f9d6e6e2c Mon Sep 17 00:00:00 2001 From: Pratik Prajapati Date: Fri, 11 Jan 2019 14:00:40 -0800 Subject: soc/intel/skylake: Access conf pointer only if its not null conf pointer could be null, access it only if its not null. Foundby=klocwork BUG=N/A TEST=N/A Signed-off-by: Pratik Prajapati Change-Id: I0611e15d52edd8e69e4234b8ac602f35efba4015 Reviewed-on: https://review.coreboot.org/c/30862 Tested-by: build bot (Jenkins) Reviewed-by: Lijian Zhao --- src/soc/intel/skylake/cpu.c | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) (limited to 'src/soc/intel/skylake/cpu.c') diff --git a/src/soc/intel/skylake/cpu.c b/src/soc/intel/skylake/cpu.c index 0f0518aeaf..413fbbb130 100644 --- a/src/soc/intel/skylake/cpu.c +++ b/src/soc/intel/skylake/cpu.c @@ -3,7 +3,7 @@ * * Copyright (C) 2007-2009 coresystems GmbH * Copyright (C) 2014 Google Inc. - * Copyright (C) 2015-2017 Intel Corporation. + * Copyright (C) 2015-2019 Intel Corporation. * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by @@ -248,7 +248,7 @@ static void configure_thermal_target(void) /* Set TCC activation offset if supported */ msr = rdmsr(MSR_PLATFORM_INFO); - if ((msr.lo & (1 << 30)) && conf->tcc_offset) { + if ((msr.lo & (1 << 30)) && conf && conf->tcc_offset) { msr = rdmsr(MSR_TEMPERATURE_TARGET); msr.lo &= ~(0xf << 24); /* Bits 27:24 */ msr.lo |= (conf->tcc_offset & 0xf) << 24; -- cgit v1.2.3