From 038e7247dc9705ff2d47dd90ec9a807f6feb52ba Mon Sep 17 00:00:00 2001 From: Elyes HAOUAS Date: Fri, 29 Jul 2016 18:31:16 +0200 Subject: src/soc: Capitalize CPU, ACPI, RAM and ROM Change-Id: I7f0d3400126d593bad8e78f95e6b9a378463b4ce Signed-off-by: Elyes HAOUAS Reviewed-on: https://review.coreboot.org/15963 Tested-by: build bot (Jenkins) Reviewed-by: Omar Pakker Reviewed-by: Martin Roth --- src/soc/intel/skylake/cpu.c | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) (limited to 'src/soc/intel/skylake/cpu.c') diff --git a/src/soc/intel/skylake/cpu.c b/src/soc/intel/skylake/cpu.c index b7353cab6b..2b75e5aeb4 100644 --- a/src/soc/intel/skylake/cpu.c +++ b/src/soc/intel/skylake/cpu.c @@ -352,7 +352,7 @@ static void cpu_core_init(device_t cpu) /* Clear out pending MCEs */ configure_mca(); - /* Enable the local cpu apics */ + /* Enable the local CPU apics */ enable_lapic_tpr(); setup_lapic(); @@ -487,7 +487,7 @@ int soc_skip_ucode_update(u32 current_patch_id, u32 new_patch_id) * 0x08b with the Patch revision id one less than the id in the * microcode binary. The PRMRR support is indicated in the MSR * MTRRCAP[12]. Check for this feature and avoid reloading the - * same microcode during cpu initialization. + * same microcode during CPU initialization. */ msr = rdmsr(MTRR_CAP_MSR); return (msr.lo & PRMRR_SUPPORTED) && (current_patch_id == new_patch_id - 1); -- cgit v1.2.3