From 6b45ee44a9bbccb4dc42ea454aa20ef7d02a9fd1 Mon Sep 17 00:00:00 2001 From: Subrata Banik Date: Fri, 12 May 2017 11:43:57 +0530 Subject: soc/intel/skylake: Add option to enable/disable EIST Set MSR 0x1A0 bit[16] based on EIST config option. Default Hardware Managed P-state (HWP) also known as Intel Speed Shift is enabled on SKL hence disable EIST and ACPI P-state table. Change-Id: I2b7374a8a04b596edcc88165b64980b7aa09e2a7 Signed-off-by: Subrata Banik Reviewed-on: https://review.coreboot.org/19676 Tested-by: build bot (Jenkins) Reviewed-by: Aaron Durbin Reviewed-by: Paul Menzel --- src/soc/intel/skylake/chip_fsp20.c | 3 +++ 1 file changed, 3 insertions(+) (limited to 'src/soc/intel/skylake/chip_fsp20.c') diff --git a/src/soc/intel/skylake/chip_fsp20.c b/src/soc/intel/skylake/chip_fsp20.c index 2d9b864629..8a7cb210e0 100644 --- a/src/soc/intel/skylake/chip_fsp20.c +++ b/src/soc/intel/skylake/chip_fsp20.c @@ -261,6 +261,9 @@ void platform_fsp_silicon_init_params_cb(FSPS_UPD *supd) /* Enable PMC XRAM read */ tconfig->PchPmPmcReadDisable = config->PchPmPmcReadDisable; + /* Enable/Disable EIST */ + tconfig->Eist = config->eist_enable; + soc_irq_settings(params); } -- cgit v1.2.3