From 0da186c3ffb1d9aa7433a5d0d5263aba7a25ad60 Mon Sep 17 00:00:00 2001 From: Rizwan Qureshi Date: Thu, 23 Feb 2017 14:43:39 +0530 Subject: soc/intel/skylake: indicate voltage margining enabled/disabled Support for voltage margining is dependent on the platform. Enabling voltage margining puts additional constraints for the SLP_S0# to be asserted and hence moving to S0ix state. If the platform PMIC/VR supports PCH voltage reduction, voltage marigining can be enabled. Use the UPD provided by FSP to enable/disable voltage margining. Change-Id: Iea214e9d7d6126e8367426485c6446ced63caa66 Signed-off-by: Rizwan Qureshi Reviewed-on: https://review.coreboot.org/18469 Tested-by: build bot (Jenkins) Reviewed-by: Paul Menzel Reviewed-by: Aaron Durbin --- src/soc/intel/skylake/chip_fsp20.c | 4 ++++ 1 file changed, 4 insertions(+) (limited to 'src/soc/intel/skylake/chip_fsp20.c') diff --git a/src/soc/intel/skylake/chip_fsp20.c b/src/soc/intel/skylake/chip_fsp20.c index 8b8c37c031..929aa5be7b 100644 --- a/src/soc/intel/skylake/chip_fsp20.c +++ b/src/soc/intel/skylake/chip_fsp20.c @@ -220,6 +220,10 @@ void platform_fsp_silicon_init_params_cb(FSPS_UPD *supd) params->PchPmPwrBtnOverridePeriod = config->PmConfigPwrBtnOverridePeriod; params->PchPmPwrCycDur = config->PmConfigPwrCycDur; + + /* Indicate whether platform supports Voltage Margining */ + params->PchPmSlpS0VmEnable = config->PchPmSlpS0VmEnable; + params->PchSirqEnable = config->SerialIrqConfigSirqEnable; params->PchSirqMode = config->SerialIrqConfigSirqMode; -- cgit v1.2.3