From 6b45ee44a9bbccb4dc42ea454aa20ef7d02a9fd1 Mon Sep 17 00:00:00 2001
From: Subrata Banik <subrata.banik@intel.com>
Date: Fri, 12 May 2017 11:43:57 +0530
Subject: soc/intel/skylake: Add option to enable/disable EIST

Set MSR 0x1A0 bit[16] based on EIST config option.
Default Hardware Managed P-state (HWP) also known as Intel Speed Shift
is enabled on SKL hence disable EIST and ACPI P-state table.

Change-Id: I2b7374a8a04b596edcc88165b64980b7aa09e2a7
Signed-off-by: Subrata Banik <subrata.banik@intel.com>
Reviewed-on: https://review.coreboot.org/19676
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
---
 src/soc/intel/skylake/chip.h | 6 ++++++
 1 file changed, 6 insertions(+)

(limited to 'src/soc/intel/skylake/chip.h')

diff --git a/src/soc/intel/skylake/chip.h b/src/soc/intel/skylake/chip.h
index b474ca22a1..43c921e8e6 100644
--- a/src/soc/intel/skylake/chip.h
+++ b/src/soc/intel/skylake/chip.h
@@ -459,6 +459,12 @@ struct soc_intel_skylake_config {
 
 	/* Enable SGX feature */
 	u8 sgx_enable;
+
+	/* Enable/Disable EIST
+	 * 1b - Enabled
+	 * 0b - Disabled
+	 */
+	u8 eist_enable;
 };
 
 typedef struct soc_intel_skylake_config config_t;
-- 
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