From 6ab4ed40d355a55f0ff8e8aade55be796a256c0d Mon Sep 17 00:00:00 2001 From: Rizwan Qureshi Date: Tue, 5 Sep 2017 14:18:25 +0530 Subject: soc/intel/skylake: Add config for enabling PCIe AER Add a config for enabling/disabling Advanced Error Reporting feature for PCIe root ports. BUG=b:64798078 TEST="lspci" shows that AER is enabled in the capabilities list. Change-Id: Ieb74c3566ded2276e549c98f78813c4f5d4d310a Signed-off-by: Rizwan Qureshi Reviewed-on: https://review.coreboot.org/21401 Tested-by: build bot (Jenkins) Reviewed-by: Paul Menzel Reviewed-by: Aaron Durbin Reviewed-by: Furquan Shaikh --- src/soc/intel/skylake/chip.h | 1 + 1 file changed, 1 insertion(+) (limited to 'src/soc/intel/skylake/chip.h') diff --git a/src/soc/intel/skylake/chip.h b/src/soc/intel/skylake/chip.h index beb5a7aa0b..45f3f9982a 100644 --- a/src/soc/intel/skylake/chip.h +++ b/src/soc/intel/skylake/chip.h @@ -173,6 +173,7 @@ struct soc_intel_skylake_config { u8 PcieRpEnable[CONFIG_MAX_ROOT_PORTS]; u8 PcieRpClkReqSupport[CONFIG_MAX_ROOT_PORTS]; u8 PcieRpClkReqNumber[CONFIG_MAX_ROOT_PORTS]; + u8 PcieRpAdvancedErrorReporting[CONFIG_MAX_ROOT_PORTS]; /* USB related */ struct usb2_port_config usb2_ports[16]; -- cgit v1.2.3