From c25c1ebd9ed54d9c70d4c247c71fc19259751413 Mon Sep 17 00:00:00 2001 From: Martin Roth Date: Fri, 24 Jul 2020 12:26:21 -0600 Subject: src: Update bare access to BOOL CONFIG_ vals to CONFIG() BOOL type Kconfig values should be used through the CONFIG() macro. These instances were not, so update them. Signed-off-by: Martin Roth Change-Id: Ie4706d82c12c487607bbf5ad8059922e0e586858 Reviewed-on: https://review.coreboot.org/c/coreboot/+/43825 Tested-by: build bot (Jenkins) Reviewed-by: Angel Pons --- src/soc/intel/skylake/chip.c | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) (limited to 'src/soc/intel/skylake/chip.c') diff --git a/src/soc/intel/skylake/chip.c b/src/soc/intel/skylake/chip.c index 52e4d3061c..f14a163772 100644 --- a/src/soc/intel/skylake/chip.c +++ b/src/soc/intel/skylake/chip.c @@ -223,7 +223,7 @@ void platform_fsp_silicon_init_params_cb(FSPS_UPD *supd) memset(params->PcieRpPmSci, 0, sizeof(params->PcieRpPmSci)); /* Legacy 8254 timer support */ - params->Early8254ClockGatingEnable = !CONFIG_USE_LEGACY_8254_TIMER; + params->Early8254ClockGatingEnable = !CONFIG(USE_LEGACY_8254_TIMER); memcpy(params->SerialIoDevMode, config->SerialIoDevMode, sizeof(params->SerialIoDevMode)); @@ -328,7 +328,7 @@ void platform_fsp_silicon_init_params_cb(FSPS_UPD *supd) params->PchSirqEnable = config->serirq_mode != SERIRQ_OFF; params->PchSirqMode = config->serirq_mode == SERIRQ_CONTINUOUS; - params->CpuConfig.Bits.SkipMpInit = !CONFIG_USE_INTEL_FSP_MP_INIT; + params->CpuConfig.Bits.SkipMpInit = !CONFIG(USE_INTEL_FSP_MP_INIT); for (i = 0; i < ARRAY_SIZE(config->i2c_voltage); i++) params->SerialIoI2cVoltage[i] = config->i2c_voltage[i]; -- cgit v1.2.3