From e7ceae79502705a8dc86943e6296fd2cf7735677 Mon Sep 17 00:00:00 2001 From: Subrata Banik Date: Wed, 8 Mar 2017 17:59:40 +0530 Subject: soc/intel/skylake: Use common PCR module This patch use common PCR library to perform CRRd and CRWr operation using Port Ids, define inside soc/pcr_ids.h Change-Id: Id9336883514298e7f93fbc95aef8228202aa6fb9 Signed-off-by: Subrata Banik Reviewed-on: https://review.coreboot.org/18674 Tested-by: build bot (Jenkins) Reviewed-by: Aaron Durbin --- src/soc/intel/skylake/bootblock/pch.c | 53 +++++++++++++++++++++------------- src/soc/intel/skylake/bootblock/uart.c | 13 +++++++-- 2 files changed, 43 insertions(+), 23 deletions(-) (limited to 'src/soc/intel/skylake/bootblock') diff --git a/src/soc/intel/skylake/bootblock/pch.c b/src/soc/intel/skylake/bootblock/pch.c index 60b22dc8e4..ebd68f1988 100644 --- a/src/soc/intel/skylake/bootblock/pch.c +++ b/src/soc/intel/skylake/bootblock/pch.c @@ -18,19 +18,35 @@ #include #include #include +#include #include #include +#include #include #include #include #include -#include +#include #include #include #include -/* Max PXRC registers in ITSS*/ -#define MAX_PXRC_CONFIG 0x08 +#define PCR_DMI_LPCLGIR1 0x2730 +#define PCR_DMI_LPCLGIR2 0x2734 +#define PCR_DMI_LPCLGIR3 0x2738 +#define PCR_DMI_LPCLGIR4 0x273c + +#define PCR_DMI_ACPIBA 0x27B4 +#define PCR_DMI_ACPIBDID 0x27B8 +#define PCR_DMI_PMBASEA 0x27AC +#define PCR_DMI_PMBASEC 0x27B0 +#define PCR_DMI_TCOBASE 0x2778 + +#define PCR_DMI_LPCIOD 0x2770 +#define PCR_DMI_LPCIOE 0x2774 + +#define PCR_RTC_CONF 0x3400 +#define PCR_RTC_CONF_UCMOS_EN 0x4 /* * Enable Prefetching and Caching. @@ -69,7 +85,7 @@ static void enable_p2sbbar(void) device_t dev = PCH_DEV_P2SB; /* Enable PCR Base address in PCH */ - pci_write_config32(dev, PCI_BASE_ADDRESS_0, PCH_PCR_BASE_ADDRESS); + pci_write_config32(dev, PCI_BASE_ADDRESS_0, CONFIG_PCR_BASE_ADDRESS); /* Enable P2SB MSE */ pci_write_config8(dev, PCI_COMMAND, @@ -108,10 +124,10 @@ static void pch_enable_lpc(void) pci_write_config32(PCH_DEV_LPC, LPC_GEN4_DEC, config->gen4_dec); /* Mirror these same settings in DMI PCR */ - pcr_write32(PID_DMI, R_PCH_PCR_DMI_LPCLGIR1, config->gen1_dec); - pcr_write32(PID_DMI, R_PCH_PCR_DMI_LPCLGIR2, config->gen2_dec); - pcr_write32(PID_DMI, R_PCH_PCR_DMI_LPCLGIR3, config->gen3_dec); - pcr_write32(PID_DMI, R_PCH_PCR_DMI_LPCLGIR4, config->gen4_dec); + pcr_write32(PID_DMI, PCR_DMI_LPCLGIR1, config->gen1_dec); + pcr_write32(PID_DMI, PCR_DMI_LPCLGIR2, config->gen2_dec); + pcr_write32(PID_DMI, PCR_DMI_LPCLGIR3, config->gen3_dec); + pcr_write32(PID_DMI, PCR_DMI_LPCLGIR4, config->gen4_dec); } static void pch_interrupt_init(void) @@ -140,8 +156,7 @@ static void pch_interrupt_init(void) pch_interrupt_routing[index] > 2 && pch_interrupt_routing[index] != 8 && pch_interrupt_routing[index] != 13) { - pcr_write8(PID_ITSS, - (R_PCH_PCR_ITSS_PIRQA_ROUT + index), + pcr_write8(PID_ITSS, PCR_ITSS_PIRQA_ROUT + index, pch_interrupt_routing[index]); } } @@ -166,8 +181,8 @@ static void soc_config_acpibase(void) * to [0x3F, PMC PCI Offset 40h bit[15:2], 1] */ reg32 = ((0x3f << 18) | ACPI_BASE_ADDRESS | 1); - pcr_write32(PID_DMI, R_PCH_PCR_DMI_ACPIBA, reg32); - pcr_write32(PID_DMI, R_PCH_PCR_DMI_ACPIBDID, 0x23A0); + pcr_write32(PID_DMI, PCR_DMI_ACPIBA, reg32); + pcr_write32(PID_DMI, PCR_DMI_ACPIBDID, 0x23A0); } static void soc_config_pwrmbase(void) @@ -195,10 +210,10 @@ static void soc_config_pwrmbase(void) * implication of making sure the memory allocated to PWRMBASE to be * 64KB in size. */ - pcr_write32(PID_DMI, R_PCH_PCR_DMI_PMBASEA, + pcr_write32(PID_DMI, PCR_DMI_PMBASEA, ((PCH_PWRM_BASE_ADDRESS & 0xFFFF0000) | (PCH_PWRM_BASE_ADDRESS >> 16))); - pcr_write32(PID_DMI, R_PCH_PCR_DMI_PMBASEC, 0x800023A0); + pcr_write32(PID_DMI, PCR_DMI_PMBASEC, 0x800023A0); } static void soc_config_tco(void) @@ -222,8 +237,7 @@ static void soc_config_tco(void) * Program "TCO Base Address" PCR[DMI] + 2778h[15:5, 1] * to [SMBUS PCI offset 50h[15:5], 1]. */ - pcr_write32(PID_DMI, R_PCH_PCR_DMI_TCOBASE, - (TCO_BASE_ADDDRESS | (1 << 1))); + pcr_write32(PID_DMI, PCR_DMI_TCOBASE, TCO_BASE_ADDDRESS | (1 << 1)); /* Program TCO timer halt */ tcobase = pci_read_config16(PCH_DEV_SMBUS, TCOBASE); @@ -236,8 +250,7 @@ static void soc_config_tco(void) static void soc_config_rtc(void) { /* Enable upper 128 bytes of CMOS */ - pcr_andthenor32(PID_RTC, R_PCH_PCR_RTC_CONF, ~0, - B_PCH_PCR_RTC_CONF_UCMOS_EN); + pcr_or32(PID_RTC, PCR_RTC_CONF, PCR_RTC_CONF_UCMOS_EN); } static void enable_heci(void) @@ -269,12 +282,12 @@ void pch_early_iorange_init(void) /* IO Decode Range */ lpc_en = COMA_RANGE | (COMB_RANGE << 4); pci_write_config16(PCH_DEV_LPC, LPC_IO_DEC, lpc_en); - pcr_write16(PID_DMI, R_PCH_PCR_DMI_LPCIOD, lpc_en); + pcr_write16(PID_DMI, PCR_DMI_LPCIOD, lpc_en); /* IO Decode Enable */ lpc_en = CNF1_LPC_EN | COMA_LPC_EN | KBC_LPC_EN | MC_LPC_EN; pci_write_config16(PCH_DEV_LPC, LPC_EN, lpc_en); - pcr_write16(PID_DMI, R_PCH_PCR_DMI_LPCIOE, lpc_en); + pcr_write16(PID_DMI, PCR_DMI_LPCIOE, lpc_en); } void pch_early_init(void) diff --git a/src/soc/intel/skylake/bootblock/uart.c b/src/soc/intel/skylake/bootblock/uart.c index ff1687c520..d51d179577 100644 --- a/src/soc/intel/skylake/bootblock/uart.c +++ b/src/soc/intel/skylake/bootblock/uart.c @@ -18,13 +18,20 @@ #include #include #include +#include #include #include #include -#include +#include #include #include +/* Serial IO UART controller legacy mode */ +#define PCR_SERIAL_IO_GPPRVRW7 0x618 +#define PCR_SIO_PCH_LEGACY_UART0 (1 << 0) +#define PCR_SIO_PCH_LEGACY_UART1 (1 << 1) +#define PCR_SIO_PCH_LEGACY_UART2 (1 << 2) + /* UART2 pad configuration. Support RXD and TXD for now. */ static const struct pad_config uart2_pads[] = { /* UART2_RXD */ PAD_CFG_NF(GPP_C20, NONE, DEEP, NF1), @@ -64,8 +71,8 @@ void pch_uart_init(void) /* Put UART2 in byte access mode for 16550 compatibility */ if (!IS_ENABLED(CONFIG_DRIVERS_UART_8250MEM_32)) - pcr_andthenor32(PID_SERIALIO, - R_PCH_PCR_SERIAL_IO_GPPRVRW7, 0, SIO_PCH_LEGACY_UART2); + pcr_write32(PID_SERIALIO, PCR_SERIAL_IO_GPPRVRW7, + PCR_SIO_PCH_LEGACY_UART2); gpio_configure_pads(uart2_pads, ARRAY_SIZE(uart2_pads)); } -- cgit v1.2.3