From 05a6f29d32c246569b7a0561d35ccbf49eec1fb8 Mon Sep 17 00:00:00 2001
From: Furquan Shaikh <furquan@chromium.org>
Date: Fri, 31 Mar 2017 14:02:47 -0700
Subject: soc/intel/skylake: Add support for GSPI controller

Sky Lake PCH contains two GSPI controllers. Using the common GSPI
controller driver implementation for Intel PCH, add support for GSPI
controller buses on Sky Lake/Kaby Lake.

BUG=b:35583330

Change-Id: I29b1d4d5a6ee4093f2596065ac375c06f17d33ac
Signed-off-by: Furquan Shaikh <furquan@chromium.org>
Reviewed-on: https://review.coreboot.org/19099
Tested-by: build bot (Jenkins)
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
---
 src/soc/intel/skylake/bootblock/bootblock.c | 2 ++
 1 file changed, 2 insertions(+)

(limited to 'src/soc/intel/skylake/bootblock')

diff --git a/src/soc/intel/skylake/bootblock/bootblock.c b/src/soc/intel/skylake/bootblock/bootblock.c
index c11d3d2152..f386f96360 100644
--- a/src/soc/intel/skylake/bootblock/bootblock.c
+++ b/src/soc/intel/skylake/bootblock/bootblock.c
@@ -14,6 +14,7 @@
  */
 
 #include <bootblock_common.h>
+#include <intelblocks/gspi.h>
 #include <soc/bootblock.h>
 
 asmlinkage void bootblock_c_entry(uint64_t base_timestamp)
@@ -48,4 +49,5 @@ void bootblock_soc_init(void)
 	set_max_freq();
 	pch_early_init();
 	i2c_early_init();
+	gspi_early_bar_init();
 }
-- 
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