From ecd9a94213216f2f50e501e6b27ee390928e0dbf Mon Sep 17 00:00:00 2001 From: Naresh G Solanki Date: Thu, 11 Aug 2016 14:56:28 +0530 Subject: soc/intel/skylake: Move bootblock specific code from skylake/romstage There is a lot of code that is being referred to in bootblock but resides under skylake/romstage folder. Hence move this code into skylake/bootblock, and update the relevant header files and Makefiles. TEST=Build and Boot kunimitsu. Change-Id: If94e16fe54ccb7ced9c6b480a661609bdd2dfa41 Signed-off-by: Naresh G Solanki Reviewed-on: https://review.coreboot.org/16225 Tested-by: build bot (Jenkins) Reviewed-by: Martin Roth --- src/soc/intel/skylake/bootblock/smbus.c | 47 +++++++++++++++++++++++++++++++++ 1 file changed, 47 insertions(+) create mode 100644 src/soc/intel/skylake/bootblock/smbus.c (limited to 'src/soc/intel/skylake/bootblock/smbus.c') diff --git a/src/soc/intel/skylake/bootblock/smbus.c b/src/soc/intel/skylake/bootblock/smbus.c new file mode 100644 index 0000000000..bb305d5192 --- /dev/null +++ b/src/soc/intel/skylake/bootblock/smbus.c @@ -0,0 +1,47 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2008-2009 coresystems GmbH + * Copyright (C) 2014 Google Inc. + * Copyright (C) 2015 Intel Corporation. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#include +#include +#include +#include +#include +#include +#include +#include +#include + +static const struct reg_script smbus_init_script[] = { + /* Set SMBUS I/O base address */ + REG_PCI_WRITE32(SMB_BASE, SMBUS_BASE_ADDRESS | 1), + /* Set SMBUS enable */ + REG_PCI_WRITE8(HOSTC, HST_EN), + /* Enable I/O access */ + REG_PCI_WRITE16(PCI_COMMAND, PCI_COMMAND_IO), + /* Disable interrupts */ + REG_IO_WRITE8(SMBUS_BASE_ADDRESS + SMBHSTCTL, 0), + /* Clear errors */ + REG_IO_WRITE8(SMBUS_BASE_ADDRESS + SMBHSTSTAT, 0xff), + /* Indicate the end of this array by REG_SCRIPT_END */ + REG_SCRIPT_END, +}; + +void enable_smbus(void) +{ + reg_script_run_on_dev(PCH_DEV_SMBUS, smbus_init_script); +} + -- cgit v1.2.3