From e4a8537ce20d801a5985ba6268ae83593063a4bf Mon Sep 17 00:00:00 2001
From: Subrata Banik <subrata.banik@intel.com>
Date: Sun, 24 Jul 2016 00:36:12 +0530
Subject: soc/intel/skylake: Add C entry bootblock support

List of activity performing in this patch
- early PCH programming
- early SA programming
- early CPU programming
- mainborad early gpio programming for UART and SPI
- car setup
- move chipset programming from verstage to post console

BUG=chrome-os-partner:55357
BRANCH=none
TEST=Built and booted kunimitsu till POST code 0x34

Change-Id: If20ab869de62cd4439f3f014f9362ccbec38e143
Signed-off-by: Barnali Sarkar <barnali.sarkar@intel.com>
Signed-off-by: Naveen Krishna Chatradhi <naveenkrishna.ch@intel.com>
Signed-off-by: Rizwan Qureshi <rizwan.qureshi@intel.com>
Signed-off-by: Subrata Banik <subrata.banik@intel.com>
Reviewed-on: https://review.coreboot.org/15785
Tested-by: build bot (Jenkins)
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
---
 src/soc/intel/skylake/bootblock/pch.c | 18 +++++++++++++++++-
 1 file changed, 17 insertions(+), 1 deletion(-)

(limited to 'src/soc/intel/skylake/bootblock/pch.c')

diff --git a/src/soc/intel/skylake/bootblock/pch.c b/src/soc/intel/skylake/bootblock/pch.c
index 94ed844d3b..569611502e 100644
--- a/src/soc/intel/skylake/bootblock/pch.c
+++ b/src/soc/intel/skylake/bootblock/pch.c
@@ -3,6 +3,7 @@
  *
  * Copyright (C) 2014 Google Inc.
  * Copyright (C) 2015 Intel Corporation.
+ * Copyright (C) 2016 Intel Corporation.
  *
  * This program is free software; you can redistribute it and/or modify
  * it under the terms of the GNU General Public License as published by
@@ -14,9 +15,11 @@
  * GNU General Public License for more details.
  */
 #include <arch/io.h>
+#include <soc/bootblock.h>
 #include <soc/iomap.h>
 #include <soc/lpc.h>
 #include <soc/pci_devs.h>
+#include <soc/pcr.h>
 #include <soc/spi.h>
 
 /*
@@ -51,8 +54,21 @@ static void enable_spibar(void)
 	pci_write_config8(dev, PCI_COMMAND, pcireg);
 }
 
-static void bootblock_southbridge_init(void)
+static void enable_p2sbbar(void)
+{
+	device_t dev = PCH_DEV_P2SB;
+
+	/* Enable PCR Base address in PCH */
+	pci_write_config32(dev, PCI_BASE_ADDRESS_0, PCH_PCR_BASE_ADDRESS);
+
+	/* Enable P2SB MSE */
+	pci_write_config8(dev, PCI_COMMAND,
+			  PCI_COMMAND_MASTER | PCI_COMMAND_MEMORY);
+}
+
+void bootblock_pch_early_init(void)
 {
 	enable_spibar();
 	enable_spi_prefetch();
+	enable_p2sbbar();
 }
-- 
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