From cf73c1317dd1ab62a96eb17ed6d9c8590fb4c514 Mon Sep 17 00:00:00 2001
From: Rizwan Qureshi <rizwan.qureshi@intel.com>
Date: Thu, 4 Aug 2016 20:01:12 +0530
Subject: skylake: Do FspTempRamInit only for FSP1.1 & tidy up PCH early init

Prepare Skylake for FSP2.0 support.

We do not use FSP-T in FSP2.0 driver, hence guard the
FspTempRamInit call under a switch.

In addition to the current early PCH configuration
program few more register, so all in all we do the following,
* Program and enable ACPI Base.
* Program and enable PWRM Base.
* Program TCO Base.
* Program Interrupt configuration registers.
* Program LPC IO decode range.
* Program SMBUS Base address and enable it.
* Enable upper 128 bytes of CMOS.
And split the above programming into into smaller functions.

Also, as part of bootblock_pch_early_init we enable decoding
for HPET range. This is needed for FspMemoryInit to store and
retrieve a global data pointer.

And also move P2SB related definitions to a new header file.

TEST=Build and boot Kunimitsu

Change-Id: Ia201e03b745836ebb43b8d7cfc77550105c71d16
Signed-off-by: Rizwan Qureshi <rizwan.qureshi@intel.com>
Signed-off-by: Barnali Sarkar <barnali.sarkar@intel.com>
Reviewed-on: https://review.coreboot.org/16113
Tested-by: build bot (Jenkins)
Reviewed-by: Martin Roth <martinroth@google.com>
---
 src/soc/intel/skylake/bootblock/pch.c | 9 +++++++++
 1 file changed, 9 insertions(+)

(limited to 'src/soc/intel/skylake/bootblock/pch.c')

diff --git a/src/soc/intel/skylake/bootblock/pch.c b/src/soc/intel/skylake/bootblock/pch.c
index 569611502e..e7f414b721 100644
--- a/src/soc/intel/skylake/bootblock/pch.c
+++ b/src/soc/intel/skylake/bootblock/pch.c
@@ -18,6 +18,7 @@
 #include <soc/bootblock.h>
 #include <soc/iomap.h>
 #include <soc/lpc.h>
+#include <soc/p2sb.h>
 #include <soc/pci_devs.h>
 #include <soc/pcr.h>
 #include <soc/spi.h>
@@ -64,6 +65,14 @@ static void enable_p2sbbar(void)
 	/* Enable P2SB MSE */
 	pci_write_config8(dev, PCI_COMMAND,
 			  PCI_COMMAND_MASTER | PCI_COMMAND_MEMORY);
+
+	/*
+	 * Enable decoding for HPET memory address range.
+	 * HPTC_OFFSET(0x60) bit 7, when set the P2SB will decode
+	 * the High Performance Timer memory address range
+	 * selected by bits 1:0
+	 */
+	pci_write_config8(dev, HPTC_OFFSET, HPTC_ADDR_ENABLE_BIT);
 }
 
 void bootblock_pch_early_init(void)
-- 
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