From b000513741d330947bb832a5835378e35bdfb394 Mon Sep 17 00:00:00 2001
From: Lee Leahy <leroy.p.leahy@intel.com>
Date: Tue, 12 May 2015 18:19:47 -0700
Subject: soc/intel/skylake: Use Broadwell as comparision base for Skylake SOC

Use the Broadwell implementation as the comparison base for Skylake.

BRANCH=none
BUG=None
TEST=None

Change-Id: I22eb55ea89eb0d6883f98e4c72a6d243e819e6d8
Signed-off-by: Lee Leahy <leroy.p.leahy@intel.com>
Reviewed-on: http://review.coreboot.org/10340
Tested-by: build bot (Jenkins)
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
---
 src/soc/intel/skylake/bootblock/pch.c | 79 +++++++++++++++++++++++++++++++++++
 1 file changed, 79 insertions(+)
 create mode 100644 src/soc/intel/skylake/bootblock/pch.c

(limited to 'src/soc/intel/skylake/bootblock/pch.c')

diff --git a/src/soc/intel/skylake/bootblock/pch.c b/src/soc/intel/skylake/bootblock/pch.c
new file mode 100644
index 0000000000..2fa722097c
--- /dev/null
+++ b/src/soc/intel/skylake/bootblock/pch.c
@@ -0,0 +1,79 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright (C) 2014 Google Inc.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; version 2 of the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
+ */
+
+#include <arch/io.h>
+#include <soc/iomap.h>
+#include <soc/lpc.h>
+#include <soc/pci_devs.h>
+#include <soc/rcba.h>
+#include <soc/spi.h>
+
+/*
+ * Enable Prefetching and Caching.
+ */
+static void enable_spi_prefetch(void)
+{
+	u8 reg8 = pci_read_config8(PCH_DEV_LPC, 0xdc);
+	reg8 &= ~(3 << 2);
+	reg8 |= (2 << 2); /* Prefetching and Caching Enabled */
+	pci_write_config8(PCH_DEV_LPC, 0xdc, reg8);
+}
+
+
+static void map_rcba(void)
+{
+	pci_write_config32(PCH_DEV_LPC, RCBA, RCBA_BASE_ADDRESS | 1);
+}
+
+static void enable_port80_on_lpc(void)
+{
+	/* Enable port 80 POST on LPC. The chipset does this by default,
+	 * but it doesn't appear to hurt anything. */
+	u32 gcs = RCBA32(GCS);
+	gcs = gcs & ~0x4;
+	RCBA32(GCS) = gcs;
+}
+
+static void set_spi_speed(void)
+{
+	u32 fdod;
+	u8 ssfc;
+
+	/* Observe SPI Descriptor Component Section 0 */
+	SPIBAR32(SPIBAR_FDOC) = 0x1000;
+
+	/* Extract the Write/Erase SPI Frequency from descriptor */
+	fdod = SPIBAR32(SPIBAR_FDOD);
+	fdod >>= 24;
+	fdod &= 7;
+
+	/* Set Software Sequence frequency to match */
+	ssfc = SPIBAR8(SPIBAR_SSFC + 2);
+	ssfc &= ~7;
+	ssfc |= fdod;
+	SPIBAR8(SPIBAR_SSFC + 2) = ssfc;
+}
+
+static void bootblock_southbridge_init(void)
+{
+	map_rcba();
+	enable_spi_prefetch();
+	enable_port80_on_lpc();
+	set_spi_speed();
+}
-- 
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