From 7146445be9618eb47895782912af28fb627c009d Mon Sep 17 00:00:00 2001 From: Barnali Sarkar Date: Fri, 31 Mar 2017 18:11:49 +0530 Subject: soc/intel/skylake: Clean up code by using common FAST_SPI module This patch currently contains the following - 1. Use SOC_INTEL_COMMON_BLOCK_FAST_SPI kconfig for common FAST_SPI code. 2. Perform FAST_SPI programming by calling APIs from common FAST_SPI library. 3. Use common FAST_SPI header file. Change-Id: I4fc90504d322db70ed4ea644b1593cc0605b5fe8 Signed-off-by: Barnali Sarkar Reviewed-on: https://review.coreboot.org/19055 Tested-by: build bot (Jenkins) Reviewed-by: Aaron Durbin Reviewed-by: Subrata Banik Reviewed-by: Furquan Shaikh --- src/soc/intel/skylake/bootblock/pch.c | 36 ++--------------------------------- 1 file changed, 2 insertions(+), 34 deletions(-) (limited to 'src/soc/intel/skylake/bootblock/pch.c') diff --git a/src/soc/intel/skylake/bootblock/pch.c b/src/soc/intel/skylake/bootblock/pch.c index 01bff0bf33..a92e4cffba 100644 --- a/src/soc/intel/skylake/bootblock/pch.c +++ b/src/soc/intel/skylake/bootblock/pch.c @@ -18,6 +18,7 @@ #include #include #include +#include #include #include #include @@ -46,38 +47,6 @@ #define PCR_DMI_LPCIOD 0x2770 #define PCR_DMI_LPCIOE 0x2774 -/* - * Enable Prefetching and Caching. - */ -static void enable_spi_prefetch(void) -{ - u8 reg8 = pci_read_config8(PCH_DEV_SPI, 0xdc); - reg8 &= ~(3 << 2); - reg8 |= (2 << 2); /* Prefetching and Caching Enabled */ - pci_write_config8(PCH_DEV_SPI, 0xdc, reg8); -} - -static void enable_spibar(void) -{ - device_t dev = PCH_DEV_SPI; - u8 pcireg; - - /* Assign Resources to SPI Controller */ - /* Clear BIT 1-2 SPI Command Register */ - pcireg = pci_read_config8(dev, PCI_COMMAND); - pcireg &= ~(PCI_COMMAND_MASTER | PCI_COMMAND_MEMORY); - pci_write_config8(dev, PCI_COMMAND, pcireg); - - /* Program Temporary BAR for SPI */ - pci_write_config32(dev, PCI_BASE_ADDRESS_0, - SPI_BASE_ADDRESS | PCI_BASE_ADDRESS_SPACE_MEMORY); - - /* Enable Bus Master and MMIO Space */ - pcireg = pci_read_config8(dev, PCI_COMMAND); - pcireg |= PCI_COMMAND_MASTER | PCI_COMMAND_MEMORY; - pci_write_config8(dev, PCI_COMMAND, pcireg); -} - static void enable_p2sbbar(void) { device_t dev = PCH_DEV_P2SB; @@ -99,8 +68,7 @@ static void enable_p2sbbar(void) void bootblock_pch_early_init(void) { - enable_spibar(); - enable_spi_prefetch(); + fast_spi_early_init(SPI_BASE_ADDRESS); enable_p2sbbar(); } -- cgit v1.2.3