From 3d45000c9cab2e5e5cac11a0a6af9abdce8aa80d Mon Sep 17 00:00:00 2001 From: Elyes HAOUAS Date: Thu, 9 Aug 2018 18:55:58 +0200 Subject: src: Fix typo Change-Id: I689c5663ef59861f79b68220abd146144f7618de Signed-off-by: Elyes HAOUAS Reviewed-on: https://review.coreboot.org/27988 Tested-by: build bot (Jenkins) Reviewed-by: Martin Roth --- src/soc/intel/skylake/bootblock/pch.c | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) (limited to 'src/soc/intel/skylake/bootblock/pch.c') diff --git a/src/soc/intel/skylake/bootblock/pch.c b/src/soc/intel/skylake/bootblock/pch.c index 4c88ed55bf..26ea56a93a 100644 --- a/src/soc/intel/skylake/bootblock/pch.c +++ b/src/soc/intel/skylake/bootblock/pch.c @@ -124,7 +124,7 @@ static void soc_config_tco(void) pci_write_config32(PCH_DEV_SMBUS, TCOCTL, reg32); /* Program TCO Base */ - pci_write_config32(PCH_DEV_SMBUS, TCOBASE, TCO_BASE_ADDDRESS); + pci_write_config32(PCH_DEV_SMBUS, TCOBASE, TCO_BASE_ADDRESS); /* Enable TCO in SMBUS */ pci_write_config32(PCH_DEV_SMBUS, TCOCTL, reg32 | TCO_EN); @@ -133,7 +133,7 @@ static void soc_config_tco(void) * Program "TCO Base Address" PCR[DMI] + 2778h[15:5, 1] * to [SMBUS PCI offset 50h[15:5], 1]. */ - pcr_write32(PID_DMI, PCR_DMI_TCOBASE, TCO_BASE_ADDDRESS | (1 << 1)); + pcr_write32(PID_DMI, PCR_DMI_TCOBASE, TCO_BASE_ADDRESS | (1 << 1)); /* Program TCO timer halt */ tcobase = pci_read_config16(PCH_DEV_SMBUS, TCOBASE); -- cgit v1.2.3