From 29f8708fca820797a088c7e81eb830fc61b21d28 Mon Sep 17 00:00:00 2001 From: Subrata Banik Date: Thu, 13 Oct 2016 18:05:04 +0530 Subject: soc/intel/skylake: Enable HECI BAR for ME communication This patch programs and enables BAR for ME (bus:0/ device:0x16/function:0) device to have early ME communication. BUG=none BRANCH=none TEST=Verified Global Reset MEI message can able to perform platform global reset during romstage. Change-Id: I99ce0ccd42610112a361a48ba31168c9feaa0332 Signed-off-by: Subrata Banik Reviewed-on: https://review.coreboot.org/17016 Tested-by: build bot (Jenkins) Reviewed-by: Aaron Durbin Reviewed-by: Paul Menzel --- src/soc/intel/skylake/bootblock/pch.c | 23 +++++++++++++++++++++++ 1 file changed, 23 insertions(+) (limited to 'src/soc/intel/skylake/bootblock/pch.c') diff --git a/src/soc/intel/skylake/bootblock/pch.c b/src/soc/intel/skylake/bootblock/pch.c index 22ab1090b8..57b5fedb24 100644 --- a/src/soc/intel/skylake/bootblock/pch.c +++ b/src/soc/intel/skylake/bootblock/pch.c @@ -251,6 +251,27 @@ static void soc_config_rtc(void) B_PCH_PCR_RTC_CONF_UCMOS_EN); } +static void enable_heci(void) +{ + device_t dev = PCH_DEV_ME; + u8 pcireg; + + /* Assign Resources to HECI1 */ + /* Clear BIT 1-2 of Command Register */ + pcireg = pci_read_config8(dev, PCI_COMMAND); + pcireg &= ~(PCI_COMMAND_MASTER | PCI_COMMAND_MEMORY); + pci_write_config8(dev, PCI_COMMAND, pcireg); + + /* Program Temporary BAR for HECI1 */ + pci_write_config32(dev, PCI_BASE_ADDRESS_0, HECI1_BASE_ADDRESS); + pci_write_config32(dev, PCI_BASE_ADDRESS_1, 0x0); + + /* Enable Bus Master and MMIO Space */ + pcireg = pci_read_config8(dev, PCI_COMMAND); + pcireg |= PCI_COMMAND_MASTER | PCI_COMMAND_MEMORY; + pci_write_config8(dev, PCI_COMMAND, pcireg); +} + void pch_early_init(void) { /* @@ -281,4 +302,6 @@ void pch_early_init(void) enable_smbus(); soc_config_rtc(); + + enable_heci(); } -- cgit v1.2.3