From 1914337936dde751fe43735a62b7222861f7fcec Mon Sep 17 00:00:00 2001 From: Subrata Banik Date: Tue, 4 Jul 2017 15:56:41 +0530 Subject: soc/intel/skylake: Perform PCR read after all PCR write BIOS must ensure to read same PCR offset after PCR write operation is done. BUG=b:35587084 BRANCH=eve TEST=manual stress testing of D0<->D3 transition on eve failing unit. No hard hang with this fix. Change-Id: Id3d567aab517b16ff99a526fc29c2d71bf4042d0 Signed-off-by: Subrata Banik Reviewed-on: https://review.coreboot.org/20461 Tested-by: build bot (Jenkins) Reviewed-by: Aaron Durbin Reviewed-by: Furquan Shaikh Reviewed-by: Paul Menzel --- src/soc/intel/skylake/acpi/pcr.asl | 16 ++++++++++++++++ 1 file changed, 16 insertions(+) (limited to 'src/soc/intel/skylake/acpi') diff --git a/src/soc/intel/skylake/acpi/pcr.asl b/src/soc/intel/skylake/acpi/pcr.asl index 4b8576b804..c73830fe46 100644 --- a/src/soc/intel/skylake/acpi/pcr.asl +++ b/src/soc/intel/skylake/acpi/pcr.asl @@ -53,6 +53,14 @@ Method (PCRA, 3, Serialized) DATA, 32 } And (DATA, Arg2, DATA) + + /* + * After every write one needs to read an innocuous register + * to ensure the writes are completed for certain ports. This is done + * for all ports so that the callers don't need the per-port knowledge + * for each transaction. + */ + PCRR (Arg0, Arg1) } /* @@ -69,4 +77,12 @@ Method (PCRO, 3, Serialized) DATA, 32 } Or (DATA, Arg2, DATA) + + /* + * After every write one needs to read an innocuous register + * to ensure the writes are completed for certain ports. This is done + * for all ports so that the callers don't need the per-port knowledge + * for each transaction. + */ + PCRR (Arg0, Arg1) } -- cgit v1.2.3