From e32da955b3a4e9674c6c5012e895c79c2696032e Mon Sep 17 00:00:00 2001 From: Duncan Laurie Date: Thu, 27 Aug 2015 17:09:02 -0700 Subject: skylake: ACPI: Clean up and fix XHCI ACPI Device - Remove the old workarounds for XHCI from broadwell - Add PMC device to expose bits needed for XHCI workarounds - Implement the new workarounds for XHCI, the first will set a bit in the XHCI MMIO and the second will send a message to the PMC if a bit is set indicating the workaround is available. - Clean up the HS/SS port defines and remove unnecessary methods to determine the port count since we only support SPT-LP. BUG=chrome-os-partner:44622,chrome-os-partner:44518 BRANCH=none TEST=build and boot on glados, verify that D0 and D3 can be made to work (by disabling unused USB and the misbehaving camera) Change-Id: I535c9d22308c45a3b9bf7e4045c3d01481acc19c Signed-off-by: Patrick Georgi Original-Commit-Id: a945f8bc2976d57373be2305c5da40a5691f1e88 Original-Change-Id: I7a57051c0a5c4f5408c2d6ff0aecf660100a1aec Original-Signed-off-by: Duncan Laurie Original-Reviewed-on: https://chromium-review.googlesource.com/295950 Original-Reviewed-by: Aaron Durbin Reviewed-on: http://review.coreboot.org/11537 Tested-by: build bot (Jenkins) Reviewed-by: Alexandru Gagniuc Reviewed-by: Aaron Durbin --- src/soc/intel/skylake/acpi/pch.asl | 3 +++ 1 file changed, 3 insertions(+) (limited to 'src/soc/intel/skylake/acpi/pch.asl') diff --git a/src/soc/intel/skylake/acpi/pch.asl b/src/soc/intel/skylake/acpi/pch.asl index f2c1a16d04..951b97a77d 100644 --- a/src/soc/intel/skylake/acpi/pch.asl +++ b/src/soc/intel/skylake/acpi/pch.asl @@ -40,6 +40,9 @@ /* PCR Access */ #include "pcr.asl" +/* PMC 0:1f.2 */ +#include "pmc.asl" + /* Serial IO */ #include "serialio.asl" -- cgit v1.2.3