From 86f23acee5e9945efe1aaf99dd6dc9deb6554b11 Mon Sep 17 00:00:00 2001 From: Duncan Laurie Date: Thu, 27 Aug 2015 16:53:45 -0700 Subject: skylake: ACPI: Move storage controllers to separate file Move the storage controller devices out of serialio.asl and into a new scs.asl file and implement the power gating workarounds for D0 and D3 transitions. BUG=chrome-os-partner:44622 BRANCH=none TEST=emerge-glados coreboot Change-Id: I43081e661b7220bfa635c2d166c3675a0ff910d6 Signed-off-by: Patrick Georgi Original-Commit-Id: e0c67b386974dedf7ad475c174c0bc75dc27e529 Original-Change-Id: Iadb395f152905f210ab0361121bbd69c9731c084 Original-Signed-off-by: Duncan Laurie Original-Reviewed-on: https://chromium-review.googlesource.com/295908 Original-Reviewed-by: Aaron Durbin Reviewed-on: http://review.coreboot.org/11535 Tested-by: build bot (Jenkins) Reviewed-by: Aaron Durbin --- src/soc/intel/skylake/acpi/pch.asl | 2 ++ 1 file changed, 2 insertions(+) (limited to 'src/soc/intel/skylake/acpi/pch.asl') diff --git a/src/soc/intel/skylake/acpi/pch.asl b/src/soc/intel/skylake/acpi/pch.asl index c72a704fc4..f2c1a16d04 100644 --- a/src/soc/intel/skylake/acpi/pch.asl +++ b/src/soc/intel/skylake/acpi/pch.asl @@ -46,6 +46,8 @@ /* SMBus 0:1f.3 */ #include "smbus.asl" +/* Storage Controllers */ +#include "scs.asl" /* USB XHCI 0:14.0 */ #include "xhci.asl" -- cgit v1.2.3