From e18e6427d0f3261f9ec361d4418b8fe1dd7cc469 Mon Sep 17 00:00:00 2001 From: Martin Roth Date: Sat, 3 Jun 2017 20:03:18 -0600 Subject: src: change coreboot to lowercase MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit The word 'coreboot' should always be written in lowercase, even at the start of a sentence. Change-Id: I7945ddb988262e7483da4e623cedf972380e65a2 Signed-off-by: Martin Roth Reviewed-on: https://review.coreboot.org/20029 Tested-by: build bot (Jenkins) Reviewed-by: Philippe Mathieu-Daudé Reviewed-by: Patrick Georgi --- src/soc/intel/skylake/acpi/globalnvs.asl | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) (limited to 'src/soc/intel/skylake/acpi/globalnvs.asl') diff --git a/src/soc/intel/skylake/acpi/globalnvs.asl b/src/soc/intel/skylake/acpi/globalnvs.asl index ab3c63ca8f..d06269f2ae 100644 --- a/src/soc/intel/skylake/acpi/globalnvs.asl +++ b/src/soc/intel/skylake/acpi/globalnvs.asl @@ -57,7 +57,7 @@ Field (GNVS, ByteAcc, NoLock, Preserve) LIDS, 8, // 0x16 - LID State PWRS, 8, // 0x17 - AC Power State CMEM, 32, // 0x18 - 0x1b - CBMEM TOC - CBMC, 32, // 0x1c - 0x1f - Coreboot Memory Console + CBMC, 32, // 0x1c - 0x1f - coreboot Memory Console PM1I, 64, // 0x20 - 0x27 - PM1 wake status bit GPEI, 64, // 0x28 - 0x2f - GPE wake status bit DPTE, 8, // 0x30 - Enable DPTF -- cgit v1.2.3