From 6b45ee44a9bbccb4dc42ea454aa20ef7d02a9fd1 Mon Sep 17 00:00:00 2001 From: Subrata Banik Date: Fri, 12 May 2017 11:43:57 +0530 Subject: soc/intel/skylake: Add option to enable/disable EIST Set MSR 0x1A0 bit[16] based on EIST config option. Default Hardware Managed P-state (HWP) also known as Intel Speed Shift is enabled on SKL hence disable EIST and ACPI P-state table. Change-Id: I2b7374a8a04b596edcc88165b64980b7aa09e2a7 Signed-off-by: Subrata Banik Reviewed-on: https://review.coreboot.org/19676 Tested-by: build bot (Jenkins) Reviewed-by: Aaron Durbin Reviewed-by: Paul Menzel --- src/soc/intel/skylake/acpi.c | 7 ++++--- 1 file changed, 4 insertions(+), 3 deletions(-) (limited to 'src/soc/intel/skylake/acpi.c') diff --git a/src/soc/intel/skylake/acpi.c b/src/soc/intel/skylake/acpi.c index e8d0c1683a..64438bdd80 100644 --- a/src/soc/intel/skylake/acpi.c +++ b/src/soc/intel/skylake/acpi.c @@ -523,9 +523,10 @@ void generate_cpu_entries(device_t device) generate_c_state_entries(is_s0ix_enable, max_c_state); - /* Generate P-state tables */ - generate_p_state_entries(core_id, - cores_per_package); + if (config->eist_enable) + /* Generate P-state tables */ + generate_p_state_entries(core_id, + cores_per_package); acpigen_pop_len(); } -- cgit v1.2.3