From d92f6127e109e5bb595b6726a9f7adb61eac2d9d Mon Sep 17 00:00:00 2001 From: Subrata Date: Tue, 14 Jul 2015 16:46:40 +0530 Subject: intel/skylake: Implemented generic SPI driver for ROM/RAMSTAGE access. Created generic library to implement SPI read, write, erase and read status functionality for both ROMSTAGE and RAMSTAGE access. BRANCH=NONE BUG=chrome-os-partner:42115 TEST=Built for sklrvp and kunimitsu and verify SPI read, write, erase success from ELOG. Change-Id: Idf4ffdb550e2a3b87059554e8825a1182b448a8a Signed-off-by: Patrick Georgi Original-Commit-Id: 74907352931db78802298fe7280a39913a37f0c2 Original-Change-Id: Ib08da1b8825e2e88641acbac3863b926ec48afd9 Original-Signed-off-by: Barnali Sarkar Original-Reviewed-on: https://chromium-review.googlesource.com/294444 Original-Reviewed-by: Aaron Durbin Original-Tested-by: Subrata Banik Original-Commit-Queue: Subrata Banik Reviewed-on: http://review.coreboot.org/11422 Tested-by: build bot (Jenkins) Reviewed-by: Aaron Durbin --- src/soc/intel/skylake/Makefile.inc | 1 + 1 file changed, 1 insertion(+) (limited to 'src/soc/intel/skylake/Makefile.inc') diff --git a/src/soc/intel/skylake/Makefile.inc b/src/soc/intel/skylake/Makefile.inc index f004769208..defb94502b 100644 --- a/src/soc/intel/skylake/Makefile.inc +++ b/src/soc/intel/skylake/Makefile.inc @@ -10,6 +10,7 @@ subdirs-y += ../../../cpu/x86/mtrr subdirs-y += ../../../cpu/x86/smm subdirs-y += ../../../cpu/x86/tsc +romstage-y += flash_controller.c romstage-y += gpio.c romstage-y += memmap.c romstage-y += pch.c -- cgit v1.2.3