From 67d487e6874b854d5f265e7cc53504ce5319423b Mon Sep 17 00:00:00 2001 From: Aaron Durbin Date: Thu, 11 Aug 2016 17:13:40 -0500 Subject: soc/intel/skylake: make SPI support early stages Using malloc() in SPI code is unnecessary as there's only one SPI device that the SoC support code handles: boot device. Therefore, use CAR to for the storage to work around the current limiations of the SPI API which expects one to return pointers to objects that are writable. Additionally, include the SPI support code as well as its dependencies in all the stages. BUG=chrome-os-partner:56151 Change-Id: I0192ab59f3555deaf6a6878cc31c059c5c2b7d3f Signed-off-by: Aaron Durbin Reviewed-on: https://review.coreboot.org/16196 Tested-by: build bot (Jenkins) Reviewed-by: Furquan Shaikh Reviewed-by: Lee Leahy --- src/soc/intel/skylake/Makefile.inc | 3 +++ 1 file changed, 3 insertions(+) (limited to 'src/soc/intel/skylake/Makefile.inc') diff --git a/src/soc/intel/skylake/Makefile.inc b/src/soc/intel/skylake/Makefile.inc index 98f2718fb7..b92eab317f 100644 --- a/src/soc/intel/skylake/Makefile.inc +++ b/src/soc/intel/skylake/Makefile.inc @@ -17,6 +17,7 @@ bootblock-y += bootblock/pch.c bootblock-y += bootblock/report_platform.c bootblock-y += bootblock/smbus.c bootblock-y += bootblock/systemagent.c +bootblock-y += flash_controller.c bootblock-$(CONFIG_UART_DEBUG) += bootblock/uart.c bootblock-$(CONFIG_UART_DEBUG) += uart_debug.c bootblock-y += gpio.c @@ -26,6 +27,8 @@ bootblock-y += pcr.c bootblock-y += pmutil.c bootblock-y += tsc_freq.c +verstage-y += flash_controller.c +verstage-y += pch.c verstage-$(CONFIG_UART_DEBUG) += uart_debug.c romstage-y += flash_controller.c -- cgit v1.2.3